Method for fabrication of a semiconductor device

• US 8,034,643 B2
• Filed: 09/19/2003
• Issued: 10/11/2011
• Est. Priority Date: 09/19/2003
• Status: Expired due to Fees

• Current Assignee: Tinggi Technologies Pte., Ltd.
• Original Assignee: Tinggi Technologies Pte., Ltd.
• Inventors: Perry, Edward Robert, Wu, Daike, Kang, Xuejun, Yuan, Shu
• Primary Examiner(s): Nguyen; Khiem D
• Application Number:
  US10/572,525
• Publication Number:
  US 20080164480A1
• Time in Patent Office: 2,944 Days
• Field of Search: 438/15, 438/26, 438/122, 438/612, 438/22, 438/29, 257/67, 257/E21.476, 257/E21.506, 257/E21.531, 257/E29.089, 257/E33.075, 257/E33.001
• US Class Current: 438/22
• CPC Class Codes: H01L 21/28575 on semiconductor bodies comprising AIIIBV compounds
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01S 5/0201 Separation of the wafer into individual elements, e.g. by dicing, cleaving, etching or directly during growth
• CPC Class Codes: H01S 5/0213 Sapphire, quartz or diamond based substrates
• CPC Class Codes: H01S 5/0217 Removal of the substrate
• CPC Class Codes: H01S 5/02461 Structure or details of the laser chip to manipulate the heat flow, e.g. passive layers in the chip with a low heat conductivity
• CPC Class Codes: H01S 5/0421 characterised by the semiconducting contacting layers electrodes H01S5/0425
• CPC Class Codes: H01S 5/32341 blue laser based on GaN or GaP

Abstract

A method for fabrication of a semiconductor device on a substrate, the semiconductor having a wafer. The method includes the steps:(a) applying a seed layer of a thermally conductive metal to the wafer;(b) electroplating a relatively thick layer of the conductive metal on the seed layer, and(c) removing the substrate. A corresponding semiconductor device is also disclosed.

Claims

1. A method for fabrication of a semiconductor device, the method including:

providing a wafer comprising a substrate with multiple epitaxial layers mounted on a substrate, the multiple epitaxial layers comprising an active region where light is able to be generated;

forming a first ohmic contact layer on a first surface of the multiple epitaxial layers, the first surface being remote from the substrate, the first ohmic contact layer comprising multiple metal layers and the first ohmic contact layer being a mirror at a junction between the first surface of the multiple epitaxial layers and the first ohmic contact layer;

coating the first ohmic contact layer with an adhesion layer prior to application of a seed layer of a thermally conductive metal, wherein the seed layer is formed on the adhesion layer by electroplating and the seed layer is patterned with photoresist patterns before the electroplating;

forming a relatively thick layer of the thermally conductive metal between the photoresist patterns and adjacent to the first ohmic contact layer, the thermally conductive metal being of sufficient thickness to provide a heat sink; and

removing the substrate.

2. A method as claimed in claim 1, wherein between the forming of the first ohmic contact layer and the forming a relatively thick layer of a thermally conductive metal, the method further comprises annealing the layers to improve adhesion, and wherein the photoresist patterns are of a height in the range 15 to 500 micrometers, a thickness in the range 3 to 500 micrometers, and a spacing in the range of 200 to 2,000 microns.

3. A method as claimed in claim 1, wherein patterning is by laser beam micro-machining of the relatively thick layer.

4. A method as claimed in claim 1, wherein the relatively thick layer is of a height no greater than the photoresist height.

5. A method as claimed in claim 1, wherein the relatively thick layer of thermally conductive metal is electroplated to a height greater than the photoresist and is subsequently thinned, thinning being by polishing or wet etching.

6. A method as claimed in claim 1, wherein after the removing of the substrate, the method further comprises forming on a second surface of the multiple epitaxial layers a second ohmic contact layer, the second ohmic contact layer being selected from the group consisting of:

opaque, transparent, and semi-transparent, the second ohmic contact layer being one of blank and patterned, bonding pads being formed on the second ohmic contact layer.

7. A method as claimed in claim 1, wherein after the removing of the substrate, the method further comprises forming an ohmic contact and subsequent processing, the subsequent processing including deposition of wire bond pads.

8. A method as claimed in claim 6, wherein the second surface is cleaned and etched before the second ohmic contact layer is deposited, the second ohmic contact layer not covering the whole area of the second surface.

9. A method as claimed in claim 6, wherein a plurality of semiconductor devices are fabricated on the wafer, and wherein after forming the second ohmic contact layer there is included testing of the semiconductor devices on the wafer, and separating the layers into individual devices.

10. A method as claimed in claim 1, wherein a plurality of semiconductor devices are fabricated on the wafer without one or more selected from the group consisting of:

lapping, polishing and dicing.

11. A method as claimed in claim 6, wherein the first ohmic contact layer is on p-type layers of the multiple epitaxial layers.

12. A method as claimed in claim 11, wherein the second ohmic contact layer is formed on n-type layers of the multiple epitaxial layers.

13. A method as claimed in claim 1, wherein after the removing of the substrate, the method further comprising

depositing dielectric films on the multiple epitaxial layers;

and

cutting openings in the dielectric films, the second ohmic contact layer, and the bond pads deposited on the multiple epitaxial layers.

14. A method as claimed in claim 1, wherein the thermally conductive metal comprises copper and the multiple epitaxial layers comprise multiple GaN-related layers.