Power device with trenches having wider upper portion than lower portion

• US 8,034,682 B2
• Filed: 09/16/2010
• Issued: 10/11/2011
• Est. Priority Date: 05/20/2003
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Herrick, Robert, Losee, Becky, Probst, Dean
• Primary Examiner(s): TRAN, LONG K
• Application Number:
  US12/884,072
• Publication Number:
  US 20110003449A1
• Time in Patent Office: 390 Days
• Field of Search: 438/171, 438/190, 438/210, 438/238, 438/239, 438/242, 438/259, 438/270, 438/561, 257/E21.549, 257/E27.091, 257/E29.257, 257/E29.26, 361/509, 361/512, 361/516, 361/519, 361/520, 361/523, 361/525, 361/528, 361/529, 29/250.3, 252/62.2
• US Class Current: 438/242
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: Y10S 257/905 Plural dram cells share common contact or common trench

Abstract

A method of forming a semiconductor device includes the following. Removing portions of a silicon layer such that a trench having sidewalls which fan out near the top of the trench to extend directly over a portion of the silicon layer is formed in the silicon layer; and forming source regions in the silicon layer adjacent the trench sidewall such that the source regions extend into the portions of the silicon layer directly over which the trench sidewalls extend.

Claims

1. A method of forming a semiconductor device, comprising:

removing portions of a silicon layer such that a plurality of trenches are formed each having sidewalls which fan out near the top of the trench to extend directly over a portion of the silicon layer adjacent each trench sidewall;

forming a first insulating layer lining the trench sidewalls;

forming a gate electrode partially filling each trench;

forming a second insulating layer in each trench, the second insulating layer extending over each gate electrode and over the portions of the silicon layer which extend directly under the trench sidewalls; and

removing exposed silicon to expose an edge of the first insulating layer in each trench, the exposed edge of the first insulating layer in each trench defining a portion of each contact opening formed between every two adjacent trenches.

2. The method of claim 1, further comprising:

forming a first region of a first conductivity type in the silicon layer, wherein the step of removing exposed silicon removes portions of the first region such that of the first region only portions adjacent each trench sidewall remain, the remaining portions of the first region adjacent each trench sidewall forming a source region of the semiconductor device.

3. The method of claim 1, wherein removing portions of a silicon layer comprises:

forming a third insulating layer over the silicon layer;

removing predefined portions of the third insulating layer to define isolated exposed surface areas of the silicon layer;

performing a first silicon etch to form a middle section of each of a plurality of trenches extending into the silicon layer from the isolated exposed surface areas of the silicon layer;

isotropically etching remaining regions of the third insulating layer to expose additional surface areas of the silicon layer; and

performing a second silicon etch to form outer sections of each trench, the outer sections of the trenches extending into the silicon layer from the additional exposed surface areas of the silicon layer, the middle section of each trench extending deeper into the silicon layer than its outer sections.

4. The method of claim 1, wherein removing portions of a silicon layer comprises:

forming a masking layer over the silicon layer, the masking layer having openings through which surface areas of the silicon layer are exposed;

isotropically etching the silicon layer through the masking layer openings so as to remove bowl-shaped portions of the silicon layer, each bowl-shaped portion having a middle portion and outer portions extending directly underneath the masking layer, the outer portions forming outer sections of corresponding trenches; and

removing additional portions of the silicon layer through the masking layer openings so as to form a middle section of the trenches which extends deeper into the silicon layer than the outer sections of the trenches.

5. The method of claim 1, wherein the step of forming a gate electrode comprises:

depositing polysilicon, the polysilicon filling the plurality of trenches; and

etching back the polysilicon.

6. The method of claim 5, wherein the polysilicon is etched back so as to be below locations on the sidewalls where the sidewalls begin to fan out.

7. The method of claim 1, wherein the silicon layer comprises a body region, and the method further comprises:

implanting impurities to form a first region in the body region, the first region extending along a surface of the body region and directly below fanned-out portions of the sidewalls.

8. The method of claim 7, further comprising:

forming the body region prior to forming the plurality of trenches.

9. The method of claim 7, wherein the body region is an epitaxial layer and the plurality of trenches extend through the body region.

10. A method of forming a semiconductor device, comprising:

removing portions of a silicon layer such that a plurality of trenches are formed each having sidewalls which fan out near the top of the trench to extend directly over a portion of the silicon layer adjacent each trench sidewall;

forming a first insulating layer lining the trench sidewalls;

forming a gate electrode partially filling each trench;

forming a second insulating layer in each trench, the second insulating layer extending over each gate electrode and over the portions of the silicon layer which extend directly under the trench sidewalls;

removing exposed portions of the silicon layer to expose an edge of the first insulating layer in each trench, the exposed edge of the first insulating layer in each trench defining a portion of each contact opening formed between every two adjacent trenches; and

depositing a metal layer extending into the contact openings.

11. The method of claim 10, further comprising:

forming a first region of a first conductivity type in the silicon layer, wherein the step of removing the exposed portions of the silicon layer removes portions of the first region such that of the first region only portions adjacent each trench sidewall remain, the remaining portions of the first region adjacent each trench sidewall forming a source region of the semiconductor device.

12. The method of claim 10, wherein removing portions of a silicon layer comprises:

forming a third insulating layer over the silicon layer;

removing predefined portions of the third insulating layer to define isolated exposed surface areas of the silicon layer;

performing a first silicon etch to form a middle section of each of a plurality of trenches extending into the silicon layer from the isolated exposed surface areas of the silicon layer;

isotropically etching remaining regions of the third insulating layer to expose additional surface areas of the silicon layer; and

performing a second silicon etch to form outer sections of each trench, the outer sections of the trenches extending into the silicon layer from the additional exposed surface areas of the silicon layer, the middle section of each trench extending deeper into the silicon layer than its outer sections.

13. The method of claim 10, wherein removing portions of a silicon layer comprises:

forming a masking layer over the silicon layer, the masking layer having openings through which surface areas of the silicon layer are exposed;

isotropically etching the silicon layer through the masking layer openings so as to remove bowl-shaped portions of the silicon layer, each bowl-shaped portion having a middle portion and outer portions extending directly underneath the masking layer, the outer portions forming outer sections of corresponding trenches; and

removing additional portions of the silicon layer through the masking layer openings so as to form a middle section of the trenches which extends deeper into the silicon layer than the outer sections of the trenches.

14. The method of claim 10, wherein the step of forming a gate electrode comprises:

depositing polysilicon, the polysilicon filling the plurality of trenches; and

etching back the polysilicon.

15. The method of claim 14, wherein the polysilicon is etched back so as to be below locations on the sidewalls where the sidewalls begin to fan out.

16. The method of claim 10, wherein the silicon layer comprises a body region, and the method further comprises:

implanting impurities to form a first region in the body region, the first region extending along a surface of the body region and directly below fanned-out portions of the sidewalls.

17. The method of claim 16, further comprising:

forming the body region prior to forming the plurality of trenches.

18. The method of claim 16, wherein the body region is an epitaxial layer and the plurality of trenches extend through the body region.