SIC power DMOSFET with self-aligned source contact

• US 8,035,112 B1
• Filed: 04/23/2009
• Issued: 10/11/2011
• Est. Priority Date: 04/23/2008
• Status: Expired due to Fees

• Current Assignee: The Trustees of Purdue University (d/b/a Purdue University)
• Original Assignee: Purdue Research Foundation (The Trustees of Purdue University (d/b/a Purdue University))
• Inventors: Saha, Asmita, Cooper, James A.
• Primary Examiner(s): Dang; Phuc
• Application Number:
  US12/429,176
• Time in Patent Office: 901 Days
• Field of Search: 257/76, 257/77, 257/E21.065, 438/105, 438/142
• US Class Current: 257/77
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/5446 Located in scribe lines
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An intermediate product in the fabrication of a MOSFET, including a silicon carbide wafer having a substrate and a drift layer on said substrate, said drift layer having a plurality of source regions formed adjacent an upper surface thereof; a first oxide layer on said upper surface of said drift layer; a plurality of polysilicon gates above said first oxide layer, said plurality of polysilicon gates including a first gate adjacent a first of said source regions; an oxide layer over said first source region of greater thickness than said first oxide layer; and, an oxide layer over said first gate of substantially greater thickness than said oxide layer over said first source region.

Claims

1. A silicon carbide power MOSFET, comprising:

a silicon carbide wafer having a substrate and a drift layer on said substrate, said drift layer having a plurality of source regions formed adjacent an upper surface thereof;

a plurality of polysilicon gates above said drift layer, said plurality of polysilicon gates including a first gate adjacent a first of said source regions, said first gate having a top surface, a lower surface and a sidewall, said sidewall overlying said first source region;

a first oxide layer between said first gate lower surface and said upper surface of said drift layer;

a second, thicker oxide layer over said top surface and sidewall of said first gate; and

a conformal layer of metal extending laterally across said first gate top surface and sidewall and said adjacent first source region.

2. A silicon carbide MOSFET structure, comprising:

a silicon carbide wafer having a substrate body having a source region formed adjacent an upper surface thereof;

first and second oxide layers on said upper surface adjacent said source region;

a polysilicon gate above each of said first and second oxide layers;

a gate oxide layer, thicker than said first and second oxide layers beneath said gates, over each of said gates and the sides thereof; and

a metal or oxide layer over said source region, extending between adjacent gate oxide layers.

3. The silicon carbide MOSFET structure of claim 2, wherein said layer over said source region is a conformal layer of metal extending laterally across said gates and said source region.

4. A silicon carbide MOSFET structure, comprising:

a silicon carbide wafer having a substrate body having a source region formed adjacent an upper surface thereof;

first and second oxide layers on said upper surface adjacent said source region;

a polysilicon gate above each of said first and second oxide layers;

a gate oxide layer, thicker than said first and second oxide layers beneath said gates, over each of said gates and the sides thereof;

a metal or oxide layer over said source region, extending between adjacent gate oxide layers; and

wherein said layer over said source region is an oxide layer of greater thickness than said first and second oxide layers and substantially less thickness than said gate oxide layers.

5. A silicon carbide MOSFET structure, comprising:

a silicon carbide wafer having a substrate body having a source region formed adjacent an upper surface thereof;

first and second oxide layers on said upper surface adjacent said source region;

a polysilicon gate above each of said first and second oxide layers;

a gate oxide layer, thicker than said first and second oxide layers beneath said gates, over each of said gates and the sides thereof;

a metal or oxide layer over said source region, extending between adjacent gate oxide layers; and

wherein said MOSFET structure has a first state in which said layer over said source region is an oxide layer of greater thickness than said first and second oxide layers and substantially less thickness than said gate oxide layers, and a second state in which said layer over said source region is a conformal layer of metal extending laterally across said gates and said source region.

6. A MOSFET structure, comprising:

a silicon carbide wafer having a substrate body with an upper surface, said substrate body having at least one source region formed adjacent said upper surface;

a substrate surface oxidation layer on said upper surface of said substrate body and adjacent said source region;

at least two polysilicon gates above said substrate surface oxidation layer, said gates each having a top, a bottom and sides, wherein a first source region of said at least one source region is juxtaposed between first and second adjacent gates of said at least two polysilicon gates;

a gate oxide layer, thicker than said substrate surface oxidation layer, over said tops and sides of each of said gates; and

a material layer over said first source region and between said gate oxide layers on said sides of said gates, said material layer comprising one of an oxide and a metal contact.

7. The MOSFET structure of claim 6, wherein said gate oxide layer is more than eight times thicker than said substrate surface oxidation layer.

8. The MOSFET structure of claim 6, wherein said material layer is a source oxide layer having a thickness greater than that of said substrate surface oxidation layer and less than that of said gate oxide layer.

9. The MOSFET structure of claim 8, wherein said source oxide layer includes a first layer homogeneously formed with and of the same thickness as said substrate surface oxidation layer and a second, separately formed layer homogeneously formed with and of lesser thickness than said gate oxide layer.

10. The MOSFET structure of claim 6, wherein said material layer is a metal contact layer providing external electrical contact with said at least one source region.

11. The MOSFET structure of claim 10 wherein said metal contact layer extends over substantially the entire MOSFET structure except for at least one gate contact access portion, said metal contact layer being in electrical contact with said at least one source region but electrically insulated from said at least two polysilicon gates by at least one of said gate oxide layer and said substrate surface oxidation layer.

12. The MOSFET structure of claim 10, wherein said metal contact layer extends over said gates and covers the space between them, said metal contact layer being in electrical contact with said at least one source region but electrically insulated from said gates by at least one of said gate oxide layer and said substrate surface oxidation layer.

13. The MOSFET structure of claim 6, wherein said substrate body includes a lower, heavily doped substrate and a lightly doped superjacent drift layer.

14. The MOSFET structure of claim 13, wherein said at least one source region is defined in said drift layer.

15. The MOSFET structure of claim 6, wherein said substrate body includes a lower, heavily doped substrate, a lightly doped drift layer superjacent to said substrate, and a current spreading layer (CSL) that is superjacent to said drift layer and that is more heavily doped than said drift layer, but not as heavily doped as said substrate.

16. The MOSFET structure of claim 15, wherein said at least one source region is defined in said current spreading layer (CSL).