Display device and semiconductor device

• US 8,035,132 B2
• Filed: 07/10/2006
• Issued: 10/11/2011
• Est. Priority Date: 10/03/2001
• Status: Active Grant

• Current Assignee: HannStar Display Corporation
• Original Assignee: NEC Corporation
• Inventors: Haga, Hiroshi, Takatori, Kenichi, Asada, Hideki
• Primary Examiner(s): Hjerpe; Richard
• Assistant Examiner(s): Edwards; Carolyn R
• Application Number:
  US11/456,481
• Publication Number:
  US 20060237727A1
• Time in Patent Office: 1,919 Days
• Field of Search: 345 87-103, 345204-205, 345/690
• US Class Current: 257/204
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/08 Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 2310/06 Details of flat display driving waveforms
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2330/06 Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
• CPC Class Codes: G09G 2370/08 Details of image data interface between the display device controller and the data line driver circuit
• CPC Class Codes: G09G 3/2011 by amplitude modulation
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04

Abstract

A display device of high definition, multiple colors and low power consumption includes a display panel having a pixel section in which pixels are arrayed in the form of a matrix at the cross points of a plurality of data lines and a plurality of scanning lines, a scanning circuit for applying voltage sequentially to the plurality of scanning lines, and a data-line driver, which receives display data supplied by a host device, for applying signals corresponding to the display data to the plurality of data lines. Provided external to the display panel is a controller IC having a display memory for storing display data corresponding to the pixel section, an output buffer for reading data out of the display memory and outputting this data to the display panel, and a controller for controlling the display memory and output buffer and communication with the host device. The display panel is provided with a digital/analog converter, which forms part of the data-line driver, for converting display data represented by a digital signal to an analog signal. The width of a bus for data transfer between the controller IC and data-line driver of the display panel is such that data of a greater number of bits is transferred in parallel by a single transfer than is transferred by the bus between the controller and the host device. This allows the operating frequency of the data-line driver to be reduced.

Claims

1. A display device comprising:

an array unit in which a plurality of devices to be driven are arrayed in a form of a matrix; and

a serial/parallel converting circuit unit having more than one bit input for performing parallel processing of data for driving said devices to be driven,

said serial/parallel converting circuit unit comprising of a plurality of serial/parallel converting circuits, each having one bit input;

wherein a group of output nodes of said serial/parallel converting circuit unit are arranged along and aligned within a length of a first side of said array unit of devices to be driven, said devices adapted to be driven by a group of electric signals supplied through said first side of said array unit of device to be driven, based on a group of signals out of said group of output nodes;

wherein wirings for transferring a display signal do not intersect wirings for displaying another display signal in a section of said serial/parallel converting circuit unit.

2. A semiconductor device comprising:

an array unit in which a plurality of devices to be driven are arrayed in a form of a matrix; and

a serial/parallel converting circuit unit having more than one bit input for performing parallel processing of data for driving said devices to be driven,

said serial/parallel converting circuit unit comprising of a plurality of serial/parallel converting circuits, each having one bit input;

wherein a group of output nodes of said serial/parallel converting circuit unit are arranged along and aligned within a length of a first side of said array unit of devices to be driven, the array unit of devices are adapted to be driven by a group of electric signals supplied through said first side, based on a group of signals out of said group of output nodes,

wherein wirings for transferring a data signal do not intersect wirings for displaying another data signal in a section of said serial/parallel converting circuit unit.

3. A display device comprising a circuit, which receives display data supplied by a host device, for subjecting display data to a phase expansion;

wherein

said circuit for phase expansion of display data is arranged along and aligned within a length of a side of a display area;

in said circuit for phase expansion of display data, a number C of intersection points at which a certain signal line that transmits a signal prior to phase expansion intersects other signal lines is less than

C=n(n−

1)(k−

1)/2

where n represents degree to which supplied display data is parallel, k represents the degree to which the supplied display data is made further parallel during phase expansion and k×

n represents degree to which display data is parallel after phase expansion.

9. The display device according to claim 3 comprising:

a display device substrate including pixels arrayed in the form of a matrix in the vicinity of intersections between a plurality of data lines and a plurality of scanning lines, wherein

said display device substrate is equipped with said circuit for subjecting display data to a phase expansion.

10. The display device according to claim 9 further comprising:

a controller IC provided externally of said display device substrate; and

a data-line driver circuit that is formed on said display device substrate and applies signals corresponding to the display data to said plurality of data lines;

wherein said controller IC includes a display memory that stores display data, an output buffer that reads data out of said display memory and outputs the data to said display device substrate, and a controller that controls said display memory and said display device; and

wherein a bus for data transfer between said controller IC and said display device substrate has a width such that data of a greater number of bits is transferred in parallel per one transfer than is transferred by a bus between said controller IC and said host device.

4. A semiconductor device comprising a circuit, which receives data supplied by a host device, for subjecting said data to a phase expansion;

wherein

said circuit for phase expansion of display data is arranged along and aligned within a length of a side of a display area;

in said circuit for phase expansion of display data, a number C of intersection points at which a certain data signal line that transmits a data signal prior to phase expansion intersects other data signal lines is less than

C=n(n−

1)(k−

1)/2

where n represents degree to which supplied data is parallel, k represents the degree to which the supplied display data is made further parallel during phase expansion and k×

n represents degree to which data is parallel after phase expansion.

5. A semiconductor device comprising:

an array unit in which a plurality of devices to be driven are arrayed in a form of a matrix; and

a serial/parallel converting circuit unit having more than 1 bit input for performing parallel processing of data for driving said device to be driven,

said serial/parallel converting circuit unit comprised of a plurality of serial/parallel converting circuits, each having one bit input;

wherein a group of output nodes of said serial/parallel converting circuit unit are arranged along and aligned within a length of a first side of said array unit of devices to be driven which are adapted to be driven by a group of electric signals supplied through said first side of said array unit of device to be driven based on a group of signals output by said group of output nodes.

6. The semiconductor device according to claim 5, wherein at least two number of serial/parallel converting circuits in said serial/parallel converting circuit unit are driven synchronously by a control line connected in common to said two number of serial/parallel converting circuits.

11. A display device comprising a display device substrate and a controller IC provided externally of said display device substrate;

wherein

said display device substrate comprises said semiconductor device according to claim 5 provided that said array unit comprises a plurality of pixels arrayed in the form of a matrix in the vicinity of intersections between a plurality of data lines and a plurality of scanning lines;

a data-line driver circuit applies signals corresponding to the display data to said plurality of data lines is formed on said display device substrate;

said controller IC has a display memory that stores display data, an output buffer that reads data out of said display memory and outputs the data to said display device substrate, and a controller that controls said display memory and said display device;

a bus for data transfer between said controller IC and said display device substrate has a width such that data of a greater number of bits is transferred in parallel by one transfer than is transferred by a bus between said controller and a host device of higher ordinate.

14. The semiconductor device according to claim 5, wherein the group of output nodes are arranged along only the first side of said array unit of devices to be driven.

7. A semiconductor device comprising:

an array unit in which a plurality of devices to be driven are arrayed in a form of a matrix;

a driver circuit for writing an electric signal into said devices to be driven; and

a serial/parallel converting circuit unit having more than 1 bit input for performing parallel processing of data,

a group of output nodes for outputting a signal obtained on serial/parallel converting data supplied to a first input node of said serial/parallel converting circuit unit, and a group of output nodes for outputting a signal obtained on serial/parallel converting data supplied to a second input node, adjacent to said first input node of said serial/parallel converting circuit unit being arranged adjacent;

wherein said group of output nodes of said serial/parallel converting circuit unit are arranged along and aligned within a length of a first side of said array unit of devices to be driven which are adapted to be driven by a group of electric signals supplied through said first side of said array unit based on a group signals output by said group output nodes.

12. A display device comprising a display device substrate and a controller IC provided externally of said display device substrate, wherein

said display device substrate comprises said semiconductor device according to claim 7 provided that said array unit comprises a plurality of pixels arrayed in the form of a matrix in the vicinity of intersections between a plurality of data lines and a plurality of scanning lines,

a data-line driver circuit that applies signals corresponding to the display data to said plurality of data lines is formed on said display device substrate;

said controller IC comprises a display memory that stores display data, an output buffer that reads data out of said display memory and outputs the data to said display device substrate, and a controller that controls said display memory and said display device;

a bus for data transfer between said controller IC and said display device substrate has a width such that data of a greater number of bits is transferred in parallel per one transfer than is transferred by a bus between said controller and a host device of a higher ordinate.

15. The semiconductor device according to claim 7, wherein the group of output nodes are arranged along only the first side of said array unit of devices to be driven.

8. A semiconductor device comprising:

an array unit in which a plurality of devices to be driven are arrayed in the form of a matrix;

a driver circuit for writing an electric signal into said devices to be driven; and

a serial/parallel converting circuit unit having more than 1 bit input for performing parallel processing of data,

said serial/parallel converting circuit unit being arranged with a layout pattern having substantially a form of a rectangle, a group of input nodes of said serial/parallel converting circuit unit being provided on one of longer sides of said rectangle and a group of output nodes of said serial/parallel converting circuit unit being provided on another longer side of said rectangle; and

said serial/parallel converting circuit being formed as an integrated circuit laid-out on a substrate;

wherein said group of output nodes are arranged along and aligned within a length of a first side of said array unit of devices to be driven, and said devices to be driven are adapted to be driven by a group of electric signals supplied through said first side of said array unit based on a group signals output by said group output nodes.

13. A display device comprising a display device substrate and a controller IC provided externally of said display device substrate;

wherein

said display device substrate comprises said semiconductor device according to claim 8 provided that said array unit comprises a plurality pixels arrayed in the form of a matrix in the vicinity of intersections between a plurality of data lines and a plurality of scanning lines;

a data-line driver circuit that applies signals corresponding to the display data to said plurality of data lines is formed on said display device substrate;

said controller IC comprises a display memory that stores display data, an output buffer that reads data out of said display memory and outputs the data to said display device substrate, and a controller that controls said display memory and said display device;

a bus for data transfer between said controller IC and said display device substrate has a width such that data of a greater number of bits is transferred in parallel per one a single transfer than is transferred by a bus between said controller and a host device.

16. The semiconductor device according to claim 8, wherein the group of output nodes are arranged along only the first side of said array unit of devices to be driven.