Split-gate non-volatile memory cell and method

• US 8,035,156 B2
• Filed: 09/30/2008
• Issued: 10/11/2011
• Est. Priority Date: 09/30/2008
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Chindalore, Gowrishankar L., Gasquet, Horacio P., Winstead, Brian A., Loiko, Konstantin V.
• Primary Examiner(s): Nguyen; Dao
• Assistant Examiner(s): Nguyen; Tram H
• Application Number:
  US12/241,786
• Publication Number:
  US 20100078703A1
• Time in Patent Office: 1,106 Days
• Field of Search: 257311-321, 438257-267, 438/283, 438/304, 438/596, 438/962, 438/255, 438/256, 438/201, 438/288, 438/573, 438/652
• US Class Current: 257/324
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A method is disclosed for making a non-volatile memory cell on a semiconductor substrate. A select gate structure is formed over the substrate. The control gate structure has a sidewall. An epitaxial layer is formed on the substrate in a region adjacent to the sidewall. A charge storage layer is formed over the epitaxial layer. A control gate is formed over the charge storage layer. This allows for in-situ doping of the epitaxial layer under the select gate without requiring counterdoping. It is beneficial to avoid counterdoping because counterdoping reduces charge mobility and increases the difficulty in controlling threshold voltage. Additionally there may be formed a recess in the substrate and the epitaxial layer is formed in the recess, and a halo implant can be performed, prior to forming the epitaxial layer, through the recess into the substrate in the area under the select gate.

Claims

1. A method of making a non-volatile memory cell on a semiconductor substrate, comprising:

forming a select gate structure over the substrate wherein the select gate structure has a first sidewall; and

growing a first epitaxial layer on the substrate in a region adjacent to the first sidewall, wherein said growing the first epitaxial layer is performed subsequent to said forming the select gate structure;

forming a charge storage layer over the first epitaxial layer; and

forming a control gate over the charge storage layer.

2. The method of claim 1, forming a completed select gate from the select gate structure, wherein the select gate has a second sidewall.

3. The method of claim 2, further comprising forming a first source/drain adjacent to the second sidewall and a second source/drain adjacent to a side of the select gate that is away from the first sidewall.

4. The method of claim 1, wherein the semiconductor substrate has a first conductivity type, and wherein the step of growing the epitaxial layer includes in-situ doping to a second conductivity type.

5. The method of claim 1, further comprising forming a first recess in the semiconductor substrate adjacent to the first sidewall, wherein the step of growing the first epitaxial layer is further characterized as growing the first epitaxial layer in the first recess.

6. The method of claim 5, further comprising performing a halo implant into a region of the substrate under the select gate structure after forming the first recess and before forming the first epitaxial layer.

7. The method of claim 5, wherein the semiconductor substrate has a first conductivity type, and wherein the step of growing the epitaxial layer includes in-situ doping to a second conductivity type.

8. The method of claim 7, wherein the step of in-situ doping comprises initially in-situ doping to a first concentration followed by in-situ doping to a second concentration wherein the first concentration is greater than the second concentration.

9. The method of claim 8, wherein the step of growing the first epitaxial layer is further characterized as in-situ doping to the first conductivity type after in-situ doping to the second concentration.

10. The method of claim 5, wherein the step of forming the epitaxial layer is further characterized by the epitaxial layer being formed to be of the same semiconductor material as the semiconductor substrate.

11. The method of claim 5, wherein the step of forming the charge storage layer is further characterized by the charge storage layer comprising a nanocrystal layer.

12. The method of claim 5, wherein:

the step of forming the select gate structure is further characterized as forming the select gate to have the first sidewall and a second sidewall;

the step of forming the first recess further comprises forming a second recess in the semiconductor substrate adjacent to the second sidewall; and

the step of growing the first epitaxial layer further comprises growing a second epitaxial layer in the second recess.

13. The method of claim 12 further comprising performing a halo implant through the first recess and the second recess and into a region of the substrate under the select gate after forming the first recess and the second recess and before forming the first epitaxial layer and the second epitaxial layer.

14. A method of forming a non-volatile memory cell, comprising:

forming a select gate over a substrate;

forming a first recess in the substrate one on a first side of the select gate and a second recess in the substrate on a second side of the select gate;

growing a first epitaxial region in the first recess and a second epitaxial region in the second recess;

forming a charge storage layer over the second epitaxial region; and

forming a control gate over the charge storage layer.

15. The method of claim 14, further comprising performing a halo implant into the substrate under the select gate after the step of forming the first recess and before the step of growing.

16. The method of claim 15, wherein the substrate is further characterized as having a background doping of the first conductivity type and wherein the step of growing is further characterized as including in-situ-doping to a second conductivity type.

17. The method of claim 16, wherein the step of growing is further characterized by the first epitaxial region having a semiconductor content which is only silicon and the semiconductor substrate is further characterized by having a semiconductor content which is only silicon.

18. The method of claim 14, wherein the substrate is further characterized as having a background doping of the first conductivity type and wherein the step of growing is further characterized as including in-situ-doping to a second conductivity type.