System and method for ESD protection

• US 8,035,162 B2
• Filed: 03/22/2010
• Issued: 10/11/2011
• Est. Priority Date: 01/15/1999
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Woo, Agnes N., Kindsfater, Kenneth R., Lu, Fang
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US12/729,040
• Publication Number:
  US 20100172060A1
• Time in Patent Office: 568 Days
• Field of Search: 257/355, 257/356, 257/357, 257/360
• US Class Current: 257/355
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/0053 with means to reduce eddy currents
• CPC Class Codes: H01F 2021/125 Printed variable inductor with taps, e.g. for VCO
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12034 Varactor
• CPC Class Codes: H01L 2924/12035 Zener diode
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03D 7/161 all the frequency changers being connected in cascade
• CPC Class Codes: H03D 7/18 Modifications of frequency-changers for eliminating image frequencies H03D7/16 takes precedence
• CPC Class Codes: H03G 1/0029 using FETs
• CPC Class Codes: H03H 11/1291 Current or voltage controlled filters
• CPC Class Codes: H03J 2200/10 Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 3/08 by varying a second parameter simultaneously with the tuning, e.g. coupling bandpass filter
• CPC Class Codes: H03J 3/185 : with varactors, i.e. voltage variable reactive diodes
• CPC Class Codes: H03L 7/107 : using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
• CPC Class Codes: H03L 7/23 : with pulse counters or frequency dividers

Abstract

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.

Claims

1. An integrated circuit electrostatic discharge (ESD) protection circuit, comprising:

a shunting grounded-gate n-type metal-oxide-semiconductor (ggNMOS) ESD structure; and

a gate-boosting structure disposed in an n-well coupled between the ggNMOS ESD structure and a protected component, the gate-boosting structure comprising;

a configuration diode coupled to the protected component;

a first transistor coupled to the configuration diode and the ggNMOS ESD structure, and

a second transistor coupled to the first transistor and the configuration diode, the configuration diode, the first transistor, and the second transistor being disposed in the n-well.

2. The ESD protection circuit of claim 1, wherein the protected component comprises:

an integrated circuit bond pad, the integrated circuit bond pad including;

a first metal layer having a first surface area;

a second metal layer having a second surface area that is less than the first surface area,

wherein the first metal layer overlaps the second metal layer, and

wherein the first metal layer is connected to the second metal layer via a feed-through; and

a substrate,

wherein the first and second metal layers are disposed on the substrate and the second metal layer is located between the first metal layer and the substrate.

3. The ESD protection circuit of claim 1, wherein the protected component comprises at least one of a group consisting of:

a broadcast receiver,

a radio receiver,

a cable television set-top box,

a local area network receiver,

a testing device,

a measuring device, and

a radar receiver.

4. The ESD protection circuit of claim 1, further comprising:

a plurality of bonding pads,

wherein the ggNMOS ESD structure is disposed in between two adjacent bonding pads in the plurality of bonding pads.

5. The ESD protection circuit of claim 1, further comprising:

a ground ring, coupled to the ggNMOS ESD structure, configured to receive an ESD from the ggNMOS ESD structure.

6. The ESD protection circuit of claim 1, further comprising:

a partial ground ring structure, coupled to the ggNMOS ESD structure, configured to receive an ESD from the ggNMOS ESD structure,

wherein the partial ground ring structure includes a first terminating point and a second terminating point, the first and second terminating points defining a gap.

7. The ESD protection circuit of claim 1, wherein the protected component comprises:

a power supply ring coupled to the ggNMOS ESD structure.

8. The ESD protection circuit of claim 1, wherein the protected component comprises:

a partial power supply ring structure coupled to the ggNMOS ESD structure,

wherein the partial power supply ring structure includes a first terminating point and a second terminating point, the first and second terminating points defining a gap.

9. An integrated circuit electrostatic discharge (ESD) protection circuit, comprising:

a shunting grounded-gate n-type metal-oxide-semiconductor (ggNMOS) transistor having a source coupled to ground, a drain coupled to a protected component, and a gate coupled to a node;

a resistor coupled between ground and the node;

a second transistor having a gate coupled to the node, and a source, drain, and backgate coupled to an n-well;

a third transistor having a drain and backgate coupled to the n-well, and a source coupled to a power supply; and

a diode having a cathode coupled to the n-well and an anode coupled to the protected component.

10. The ESD protection circuit of claim 9, wherein the protected component comprises:

an integrated circuit bond pad, the integrated circuit bond pad including;

a first metal layer having a first surface area;

a second metal layer having a second surface area that is less than the first surface area,

wherein the first metal layer overlaps the second metal layer, and

wherein the first metal layer is connected to the second metal layer via a feed-through; and

a substrate,

wherein the first and second metal layers are disposed on the substrate and the second metal layer is located between the first metal layer and the substrate.

11. The ESD protection circuit of claim 9, wherein the protected component comprises at least one of a group consisting of:

a broadcast receiver,

a radio receiver,

a cable television set-top box,

a local area network receiver,

a testing device,

a measuring device, and

a radar receiver.

12. The ESD protection circuit of claim 9, further comprising:

a plurality of bonding pads, wherein the ggNMOS ESD transistor is disposed in between two adjacent bonding pads in the plurality of bonding pads.

13. The ESD protection circuit of claim 9, further comprising:

a ground ring, coupled to the source of the ggNMOS ESD transistor, configured to receive an ESD from the ggNMOS ESD structure.

14. The ESD protection circuit of claim 9, further comprising:

a partial ground ring structure, coupled to the source of the ggNMOS ESD transistor, configured to receive an ESD from the ggNMOS ESD structure,

wherein the partial ground ring structure includes a first terminating point and a second terminating point, the first and second terminating points defining a gap.

15. The ESD protection circuit of claim 9, further comprising:

a power supply ring coupled to the drain of the ggNMOS ESD transistor.

16. The ESD protection circuit of claim 9, further comprising:

a partial power supply ring structure coupled to the drain of the ggNMOS ESD transistor, wherein the partial power supply ring structure includes a first terminating point and a second terminating point, the first and second terminating points defining a gap.

17. The ESD protection circuit of claim 9, further comprising:

a fourth transistor,

wherein the drain of the ggNMOS transistor is coupled to the protected component via the fourth transistor, and

wherein a gate of the fourth transistor is coupled to a second power supply.

18. An integrated circuit electrostatic discharge (ESD) protection circuit, comprising:

a shunting grounded-gate n-type metal-oxide-semiconductor (ggNMOS) transistor having a source coupled to ground, a drain coupled to a protected component, and a gate coupled to a node;

a resistor coupled between ground and the node;

a capacitor having a first electrode coupled to the node, and a second electrode coupled to an n-well; and

a diode having a cathode coupled to the n-well and an anode coupled to the protected component.

19. The ESD protection circuit of claim 18, wherein the protected component comprises:

an integrated circuit bond pad, the integrated circuit bond pad including;

a first metal layer having a first surface area;

a second metal layer having a second surface area that is less than the first surface area,

wherein the first metal layer overlaps the second metal layer, and

wherein the first metal layer is connected to the second metal layer via a feed-through; and

a substrate,

wherein the first and second metal layers are disposed on the substrate and the second metal layer is located between the first metal layer and the substrate.

20. The ESD protection circuit of claim 18, wherein the protected component comprises at least one of a group consisting of:

a broadcast receiver,

a radio receiver,

a cable television set-top box,

a local area network receiver,

a testing device,

a measuring device, and

a radar receiver.

21. The ESD protection circuit of claim 18, further comprising:

a plurality of bonding pads,

wherein the ggNMOS ESD transistor is disposed in between two adjacent bonding pads in the plurality of bonding pads.

22. The ESD protection circuit of claim 18, further comprising:

a ground ring, coupled to the source of the ggNMOS ESD transistor, configured to receive an ESD from the ggNMOS ESD structure.

23. The ESD protection circuit of claim 18, further comprising:

a partial ground ring structure, coupled to the source of the ggNMOS ESD transistor, configured to receive an ESD from the ggNMOS ESD structure,

wherein the partial ground ring structure includes a first terminating point and a second terminating point, the first and second terminating points defining a gap.

24. The ESD protection circuit of claim 18, further comprising:

a circuit, coupled to the source of the ggNMOS ESD transistor, configured to carry a radio frequency signal.