Top layers of metal for high performance IC's

• US 8,035,227 B2
• Filed: 06/13/2008
• Issued: 10/11/2011
• Est. Priority Date: 12/21/1998
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan
• Primary Examiner(s): PIZARRO CRESPO, MARCOS D
• Application Number:
  US12/138,455
• Publication Number:
  US 20090146307A1
• Time in Patent Office: 1,215 Days
• Field of Search: 257/690, 257/700, 257/750, 257758-760, 257/780, 257/781, 257/784, 257/E23.019, 257/E23.142
• US Class Current: 257/758
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/1148 Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 23/53295 : Stacked insulating layers
• CPC Class Codes: H01L 23/60 : Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads for flip chip applications. Photoresist defined electroplating, sputter/etch, or dual and triple damascene techniques are used for forming the metal lines and via fill.

Claims

1. A semiconductor chip comprising:

a silicon substrate;

a first dielectric layer over said silicon substrate;

a transistor under said first dielectric layer;

a first interconnecting layer over said first dielectric layer;

a second interconnecting layer over said first interconnecting layer and said first dielectric layer;

a second dielectric layer between said first and second interconnecting layers;

a first contact pad over said silicon substrate;

a second contact pad over said silicon substrate;

a passivation layer over said first and second interconnecting layers and said first and second dielectric layers, wherein said passivation layer comprises a nitride layer, wherein a first opening in said passivation layer is over a first contact point of said first contact pad, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of said second contact pad, and said second contact point is at a bottom of said second opening;

a polymer layer on said passivation layer, wherein a third opening in said polymer layer is over said first contact point, and wherein a fourth opening in said polymer layer is over said second contact point, wherein said polymer layer has a thickness between 2 and 50 micrometers;

a third interconnecting layer on said polymer layer, on said first and second contact points and in said third and fourth openings, wherein said first contact point is connected to said second contact point through said third interconnecting layer, wherein said third interconnecting layer comprises an adhesion metal layer with a thickness between 0.01 and 3 micrometers, a copper-containing seed layer with a thickness between 0.05 and 3 micrometers over said adhesion metal layer, and an electroplated copper layer with a thickness between 2 and 100 micrometers over said copper-containing seed layer; and

a metal bump on said third interconnecting layer.

2. The semiconductor chip of claim 1, wherein said adhesion metal layer comprises a titanium-tungsten-alloy layer with a thickness between 0.01 and 3 micrometers.

3. The semiconductor chip of claim 1, wherein said adhesion metal layer comprises a titanium-containing layer with a thickness between 0.01 and 3 micrometers.

4. The semiconductor chip of claim 1, wherein said metal bump comprises a solder.

13. The semiconductor chip of claim 1, wherein said first adhesion metal layer comprises a titanium-tungsten-alloy layer with a thickness between 0.01 and 3 micrometers.

14. The semiconductor chip of claim 1, wherein said first adhesion metal layer comprises a titanium-nitride layer with a thickness between 0.01 and 3 micrometers.

15. The semiconductor chip of claim 1, wherein said first adhesion metal layer comprises a titanium-containing layer with a thickness between 0.01 and 3 micrometers.

16. The semiconductor chip of claim 1, wherein said second adhesion metal layer comprises a titanium-tungsten-alloy layer with a thickness between 0.01 and 3 micrometers.

17. The semiconductor chip of claim 1, wherein said second adhesion metal layer comprises a titanium-nitride layer with a thickness between 0.01 and 3 micrometers.

18. The semiconductor chip of claim 1, wherein said second adhesion metal layer comprises a titanium-containing layer with a thickness between 0.01 and 3 micrometers .

19. The semiconductor chip of claim 1 further comprising a second polymer layer with a thickness between 2 and 50 micrometers on said passivation layer, wherein said first metal layer is further on said second polymer layer.

20. The semiconductor chip of Claim 19, wherein said second polymer layer comprises polyimide.

5. A semiconductor chip comprising:

a silicon substrate;

a first dielectric layer over said silicon substrate;

a transistor under said first dielectric layer;

a first interconnecting layer over said first dielectric layer;

a second interconnecting layer over said first interconnecting layer and said first dielectric layer;

second dielectric layer between said first and second interconnecting layers;

a contact pad over said silicon substrate;

a separating layer over said first and second interconnecting layers and said first and second dielectric layers, wherein said separating layer comprises a nitride layer, wherein a first opening in said separating layer is over a first contact point of said contact pad, and said first contact point is at a bottom of said first opening;

a first metal layer on said separating layer and said first contact point, wherein there is no polymer layer between said separating layer and said first metal layer, wherein said first metal layer is connected to said first contact point through said first opening, wherein said first metal layer comprises a first bottom layer comprising a first adhesion metal layer and a first copper-containing seed layer over said first adhesion metal layer, and a first electroplated copper layer with a thickness between 2 and 100 micrometers on said first bottom layer, wherein said first bottom layer is at a bottom of said first electroplated copper layer, but not at a sidewall of said first electroplated copper layer;

a polymer layer over said separating layer and said first metal layer, wherein a second opening in said polymer layer is over a second contact point of said first metal layer; and

a second metal layer connected to said second contact point through said second opening, wherein said second metal layer comprises a second bottom layer comprising a second adhesion metal layer and a second copper-containing seed layer and a second copper-containing seed layer over said second adhesion metal layer, and a second electroplated copper layer with a thickness between 2 and 100 micrometers on said second bottom layer, wherein said second bottom layer is at a bottom of said second electroplated copper layer, but not at a sidewall of said second electroplated copper layer.

6. The semiconductor chip of claim 5, wherein said first adhesion metal layer comprises a titanium-containing layer.

7. The semiconductor chip of claim 5, wherein said second adhesion metal layer comprises a titanium-containing layer.

8. The semiconductor chip of claim 5, wherein said first adhesion metal layer has a thickness between 0.01 and 3 micrometers.

9. The semiconductor chip of claim 5, wherein said first copper-containing seed layer has a thickness between 0.05 and 3 micrometers.

10. The semiconductor chip of claim 5, wherein said second adhesion metal layer has a thickness between 0.01 and 3 micrometers.

11. The semiconductor chip of claim 5, wherein said second copper-containing seed layer has a thickness between 0.05 and 3 micrometers.

27. The semiconductor chip of claim 11, wherein said second adhesion metal layer comprises a chromium containing titanium-containing layer with a thickness between 0.01 and 3 micrometers on said third contact point.

12. A semiconductor chip comprising:

a silicon substrate;

a first dielectric layer over said silicon substrate;

a transistor under said first dielectric layer;

a first interconnecting layer over said first dielectric layer;

a second interconnecting layer over said first interconnecting layer and said first dielectric layer;

a second dielectric layer between said first and second interconnecting layers;

a contact pad over said silicon substrate;

a passivation layer over said first and second interconnecting layers and said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of said contact pad, and said first contact point is at a bottom of said first opening, wherein said passivation layer comprises a nitride layer;

a first metal layer over said passivation layer and on said first contact point, wherein said first metal layer is connected to said first contact point through said first opening, wherein said first metal layer comprises a first adhesion metal layer with a thickness between 0.01 and 3 micrometers, a first copper-containing seed layer with a thickness between 0.05 and 3 micrometers over said first adhesion metal layer, and a first electroplated copper layer with a thickness between 2 and 100 micrometers over said first copper-containing seed layer;

a first polymer layer over said passivation layer and said first metal layer, wherein a second opening in said first polymer layer is over a second contact point of said first metal layer; and

a second metal layer connected to said second contact point through said second opening, wherein said second metal layer comprises a second adhesion metal layer with a thickness between 0.01 and 3 micrometers, a second copper-containing seed layer with a thickness between 0.05 and 3 micrometers over said second adhesion metal layer, a second electroplated copper layer with a thickness between 2 and 100 micrometers over said second copper-containing seed layer, and a nickel-containing layer over said second electroplated copper layer.

21. A semiconductor chip comprising:

a silicon substrate;

a first dielectric layer over said silicon substrate;

a transistor under said first dielectric layer;

a first interconnecting layer over said first dielectric layer;

a second interconnecting layer over said first interconnecting layer and said first dielectric layer;

a second dielectric layer between said first and second interconnecting layers;

a contact pad over said silicon substrate;

a passivation layer over said first and second interconnecting layers and said first and second dielectric layers, wherein said passivation layer comprises a nitride layer, wherein a first opening in said passivation layer is over a first contact point of said contact pad, and said first contact point is at a bottom of said first opening;

a first metal layer over said passivation layer and on said first contact point, wherein said first metal layer is connected to said first contact point through said first opening, wherein said first metal layer comprises a first adhesion metal layer, a first copper-containing seed layer over said first adhesion metal layer, and a first electroplated copper layer over said first copper-containing seed layer;

a first polymer layer over said passivation layer and said first metal layer, wherein a second opening in said first polymer layer is over a second contact point of said first metal layer; and

a second metal layer connected to said second contact point through said second opening, wherein said second metal layer comprises a second adhesion metal layer with a thickness between 0.01 and 3 micrometers, a second copper-containing seed layer with a thickness between 0.05 and 3 micrometers over said second adhesion metal layer, and a second electroplated copper layer with a thickness between 2 and 100 micrometers over said second copper-containing seed layer.

22. The semiconductor chip of claim 21, wherein said first adhesion metal layer comprises a titanium-tungsten-alloy layer with a thickness between 0.01 and 3 micrometers over said passivation layer and over said first and second contact points.

23. The semiconductor chip of claim 21, wherein said first adhesion metal layer comprises a titanium-nitride layer.

24. The semiconductor chip of claim 21, wherein said first adhesion metal layer comprises a titanium-containing layer.

25. The semiconductor chip of claim 21, wherein said second adhesion metal layer comprises a chromium-containing layer with a thickness between 0.01 and 3 micrometers.

26. The semiconductor chip of claim 21, wherein said second adhesion metal layer comprises a titanium-nitride layer with a thickness between 0.01 and 3 micrometers on said third contact point.

28. The semiconductor chip of claim 21, wherein said first adhesion metal layer has a thickness between 0.01 and 3 micrometers.

29. The semiconductor chip of claim 21, wherein said first copper-containing seed layer has a thickness between 0.05 and 3 micrometers.

30. The semiconductor chip of claim 21 further comprising a second polymer layer with a thickness between 2 and 50 micrometers on said passivation layer, wherein said first metal layer is further on said second polymer layer.

31. The semiconductor chip of claim 30, wherein said second polymer layer comprises polyimide.