Oscillator amplitude control network
First Claim
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1. An amplitude control circuit, comprising:
- a first peak detector circuit configured to generate a first peak voltage signal corresponding to a first peak voltage of an input signal, wherein the first peak voltage of the input signal is a largest difference between the input signal and a first reference potential;
a second peak detector circuit configured to generate a second peak voltage signal corresponding to a second peak voltage of the input signal, wherein the second peak voltage is a largest difference between the input signal and a second reference potential; and
an output differential amplifier comprising a differential pair of output drive transistors of a first conductivity type, each output drive transistor having a drain coupled to a power supply node by a diode connected transistor of a second conductivity type, a first of the output drive transistors having a gate coupled to the first peak voltage signal and at least a first amplitude setting current source.
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Abstract
An amplitude control circuit (100) can include a peak level detect circuit (102) that generates a peak voltage signal (Vpeak′) based on a peak level of signal Xosc. An amplitude bias control circuit (104) can generate a bias voltage Vbc that can correspond to a peak amplitude of a received oscillator signal Xosc, and can change according to variations in a transistor threshold voltage due to process, operating conditions and voltage.
251 Citations
20 Claims
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1. An amplitude control circuit, comprising:
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a first peak detector circuit configured to generate a first peak voltage signal corresponding to a first peak voltage of an input signal, wherein the first peak voltage of the input signal is a largest difference between the input signal and a first reference potential; a second peak detector circuit configured to generate a second peak voltage signal corresponding to a second peak voltage of the input signal, wherein the second peak voltage is a largest difference between the input signal and a second reference potential; and an output differential amplifier comprising a differential pair of output drive transistors of a first conductivity type, each output drive transistor having a drain coupled to a power supply node by a diode connected transistor of a second conductivity type, a first of the output drive transistors having a gate coupled to the first peak voltage signal and at least a first amplitude setting current source. - View Dependent Claims (2, 3, 4, 5, 6, 9, 10)
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7. The amplitude control circuit of 6, wherein:
the amplitude control transistor comprises an n-channel transistor, and the first power supply node is a high power supply node.
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8. The amplitude control circuit of 6, wherein:
the amplitude control transistor comprises a p-channel transistor, and the first power supply node is a low power supply node.
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11. An amplitude control circuit, comprising:
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an amplifier drive current source that provides a drive current in response to a control signal at a control node; an output drive amplifier that generates the control signal in response to an amplitude bias signal; an amplitude setting circuit, comprising at least a first current source that provides a first current, the control node voltage change in response to changes in the first current; a first peak detector circuit that generates a first output voltage at a first hold node corresponding to a first peak voltage of an input signal, the first peak voltage being a largest difference between the input signal and a first reference potential; and second peak detector circuit that generates a second output voltage at a second hold node corresponding to a second peak voltage of the input signal, the second peak voltage being a largest difference between the input signal and a second reference potential. - View Dependent Claims (12, 13, 14, 15, 16)
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17. An amplitude control circuit, comprising:
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at least a first peak level detect means for detecting a peak voltage of an input signal; amplitude bias means for generating an amplitude bias voltage from a plurality of resistors coupled between a gate and a source of an amplitude bias transistor; and means for generating a current control voltage across a diode connected transistor based on amplitude bias voltage. - View Dependent Claims (18, 19, 20)
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Specification