5T high density NVDRAM cell

• US 8,036,032 B2
• Filed: 12/31/2007
• Issued: 10/11/2011
• Est. Priority Date: 12/31/2007
• Status: Expired due to Fees

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Guenther, Stefan, Scade, Andreas
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US12/006,270
• Publication Number:
  US 20090168521A1
• Time in Patent Office: 1,380 Days
• Field of Search: 365/185.08, 365/150
• US Class Current: 365/185.08
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor

Abstract

A memory circuit includes a high voltage region providing storage of a nonvolatile bit, and a low voltage region providing at least partial storage of a volatile bit. The high and low voltage regions are isolated from one another and formed by a plurality of transistors in series between a current source and a bit line.

Claims

1. A memory circuit comprising:

a high voltage region adapted to provide storage of a nonvolatile bit;

a low voltage region adapted to provide at least partial storage of a volatile bit; and

the high and low voltage regions isolated from one another and formed by a plurality of transistors in series between a current source and a bit line

and the high and low voltage regions formed by five transistors configured to switch in series between the current source and the bit line.

2. The memory circuit of claim 1, wherein the low voltage region providing at least partial storage of a volatile bit further comprises:

a single transistor of the low voltage region adapted to provide substantially all of the volatile bit charge storage via capacitive effects.

3. The memory circuit of claim 2, wherein the single transistor is a depletion mode transistor.

4. The memory circuit of claim 1, adapted such that the volatile bit storage is provided by transistors of both the low and high voltage regions.

5. The memory circuit of claim 4, wherein a transistor of the high voltage region is adapted to provide storage of the nonvolatile bit charge and partial storage of the volatile bit charge.

6. The memory circuit of claim 5, wherein the transistor adapted to provide storage of the nonvolatile bit charge and partial storage of the volatile bit charge is a SONOS transistor.

7. A method of operating a memory circuit, comprising:

causing a high voltage region providing storage of a nonvolatile bit and a low voltage region providing at least partial storage of a volatile bit to become un-isolated from one another so that the value of the volatile bit becomes represented on a bit line;

performing an operation involving the nonvolatile bit that affects the stored value of the volatile bit refreshing the stored value of the volatile bit; and

restoring the isolation between the high and low voltage regions.

8. The method of claim 7, further comprising:

operating a SONOS transistor and at least three non-SONOS transistors arranged in series between a current source and a bit line.

9. The method of claim 7, further comprising:

the nonvolatile operation one or more of an ERASE and a STORE.

10. A method of operating a memory circuit to perform a RECALL operation, comprising:

causing a high voltage region providing storage of a nonvolatile bit and a low voltage region providing storage of a volatile bit to become un-isolated from one another;

driving current from the high voltage region though the low voltage region and to a bit line when the stored nonvolatile bit is a one;

storing the value of the bit line to the volatile bit; and

restoring the isolation between the high and low voltage regions.

11. A device comprising:

a processor in communication with a memory system, the memory system comprising memory cells, one or more of the memory cells comprising

a high voltage region adapted to provide storage of a nonvolatile bit;

a low voltage region adapted to provide at least partial storage of a volatile bit; and

the high and low voltage regions isolated from one another and formed by a plurality of transistors in series between a current source and a bit line

and the high and low voltage regions formed by five transistors configured to switch in series between the current source and the bit line.

12. The device of claim 11, wherein a single transistor of the low voltage region adapted to provide substantially all of the volatile bit charge storage via capacitive effects.

13. The device of claim 12, wherein the single transistor of the low voltage region is a depletion mode transistor.

14. The memory circuit of claim 11, wherein the volatile bit charge storage is provided by transistors of both the low and high voltage regions.

15. The device of claim 14, wherein a transistor of the high voltage region is adapted to provide storage of the nonvolatile bit charge and partial storage of the volatile bit charge.

16. The device of claim 15, wherein the transistor adapted to storage of the nonvolatile bit charge and partial storage of the volatile bit charge is a SONOS transistor.