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Semiconductor memory having both volatile and non-volatile functionality and method of operating

  • US 8,036,033 B2
  • Filed: 06/09/2010
  • Issued: 10/11/2011
  • Est. Priority Date: 11/29/2006
  • Status: Active Grant
First Claim
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1. A semiconductor memory cell comprising:

  • a floating body region configured to be charged to a level indicative of a state of the memory cell to store the state as volatile memory;

    a first region in electrical contact with said floating body region;

    a second region in electrical contact with said floating body region and spaced apart from said first region;

    a floating gate or trapping layer positioned between said first and second regions and configured to receive transfer of data stored as said volatile memory and store said data as nonvolatile memory indicative of said state of the memory cell;

    a base region in electrical contact with said floating body region; and

    a control gate positioned above the floating gate or trapping layer.

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