Semiconductor memory having both volatile and non-volatile functionality and method of operating
First Claim
1. A semiconductor memory cell comprising:
- a floating body region configured to be charged to a level indicative of a state of the memory cell to store the state as volatile memory;
a first region in electrical contact with said floating body region;
a second region in electrical contact with said floating body region and spaced apart from said first region;
a floating gate or trapping layer positioned between said first and second regions and configured to receive transfer of data stored as said volatile memory and store said data as nonvolatile memory indicative of said state of the memory cell;
a base region in electrical contact with said floating body region; and
a control gate positioned above the floating gate or trapping layer.
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Accused Products
Abstract
Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a floating gate or trapping layer positioned in between the first and second locations and above a surface of the substrate and insulated from the surface by an insulating layer; the floating gate or trapping layer being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gate or trapping layer upon interruption of power to the memory cell; and a control gate positioned above the floating gate or trapping layer and a second insulating layer between the floating gate or trapping layer and the control gate.
209 Citations
27 Claims
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1. A semiconductor memory cell comprising:
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a floating body region configured to be charged to a level indicative of a state of the memory cell to store the state as volatile memory; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a floating gate or trapping layer positioned between said first and second regions and configured to receive transfer of data stored as said volatile memory and store said data as nonvolatile memory indicative of said state of the memory cell; a base region in electrical contact with said floating body region; and a control gate positioned above the floating gate or trapping layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of operating a memory cell having a floating body for storing data as volatile memory and a floating gate or trapping layer for storing data as non-volatile memory, the method comprising:
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upon initial application of power to the cell, placing said cell in an initial state comprising a volatile operational mode; setting the non-volatile memory to a predetermined state; and operating said cell as volatile memory. - View Dependent Claims (14, 15, 16, 17, 18)
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19. A method of operating a semiconductor storage device comprising a plurality of memory cells each having a floating body for storing data as volatile memory and a floating gate or trapping layer for storing data as non-volatile memory, the method comprising:
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upon initial application of power to the device, placing said cells in an initial state comprising a volatile operational mode; setting the non-volatile memory of each of said cells to a predetermined state; and operating said cells as volatile memory. - View Dependent Claims (20, 21, 22, 23, 24)
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25. A method of backup of a memory cell having a floating body for storing data as volatile memory and a floating gate or trapping layer for storing data as non-volatile memory, the method comprising:
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copying data content from said floating-body stored as volatile memory to said floating gate or trapping layer, thereby storing data content representative of a state of said cell in said floating gate or trapping layer as non-volatile memory; and maintaining power to said floating body so that the data content of said floating body also remains in volatile memory.
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26. A method of backing up a memory cell having a floating body for storing data as volatile memory and a floating gate or trapping layer for storing data as non-volatile memory, the method comprising:
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monitoring activity of said cell; and after a predetermined period of time during which said cell has remained idle, performing a shadowing operation thereby storing a state of the cell in non-volatile memory. - View Dependent Claims (27)
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Specification