Symmetrically operating single-ended input buffer devices and methods
First Claim
1. A differential amplifier comprising:
- a first voltage supply node and a second voltage supply node;
a first transistor coupled between the first and second voltage supply nodes, the first transistor having an input node configured to receive an input signal; and
a second transistor coupled between the first and second voltage supply nodes, the second transistor having a first terminal and a second input node configured to receive a reference signal, the first input node of the first transistor being capacitively coupled to the first terminal of the second transistor to charge and discharge the first terminal of the second transistor responsive to the input signal transitioning.
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Accused Products
Abstract
Embodiments are described including those pertaining to an input buffer having first and second complementary input terminals. One such input buffer has a symmetrical response to a single input signal applied to the first input terminal by mimicking the transition of a signal applied to the second input terminal in the opposite direction. The aforementioned input buffer includes two amplifier circuits structured to be complementary with respect to each other. Each of the amplifier circuits includes a first transistor having a first input node that receives an input signal transitioning across a range of high and low voltage levels, and a second transistor having a second input node that receives a reference signal. The first input node is coupled to the second transistor through a capacitor that charges and discharges the drain of the second transistor responsive to the input signal transitioning to mimic the second input node transitioning in the direction opposite to the transition of the input signal, while the reference signal at the second input node is maintained at a constant voltage level.
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Citations
24 Claims
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1. A differential amplifier comprising:
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a first voltage supply node and a second voltage supply node; a first transistor coupled between the first and second voltage supply nodes, the first transistor having an input node configured to receive an input signal; and a second transistor coupled between the first and second voltage supply nodes, the second transistor having a first terminal and a second input node configured to receive a reference signal, the first input node of the first transistor being capacitively coupled to the first terminal of the second transistor to charge and discharge the first terminal of the second transistor responsive to the input signal transitioning. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of generating an output signal by a differential amplifier, comprising:
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receiving a first input signal that transitions; receiving a second input signal, the second input signal being a reference voltage having a relatively constant magnitude; and capacitively coupling a portion of the first input signal to a node of the differential amplifier that would transition in the same direction as a transition of the input signal responsive to a transition of the second input signal in a direction opposite the direction that the first input signal transitions. - View Dependent Claims (8, 9)
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10. A differential amplifier comprising:
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an output node; a first transistor having a first terminal configured to receive a first input signal; and a second transistor having a second terminal capacitively coupled to the first terminal of the first transistor to provide a portion of the first input signal to the second transistor in a manner such that the drive strength of the differential amplifier is adjusted as an output signal is generated at the output node. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A differential amplifier comprising:
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a first amplifier circuit having an output node, the first amplifier circuit coupled to receive a first input signal, the first amplifier circuit configured to generate an output signal in response to the first input signal transitioning, the first amplifier circuit being capacitively coupled to receive a portion of the first input signal relative to the transition of the first input signal in a manner such that the rate at which the first amplifier circuit generates the output signal increases as the first input signal transitions; and a second amplifier circuit being coupled in parallel to the first amplifier circuit and coupled to the output node, the second amplifier circuit being configured complementary respective to the first amplifier circuit and further coupled to receive the first input signal, the second amplifier circuit configured to generate the output signal in response to the first input signal transitioning, the second amplifier circuit being capacitively coupled to receive a portion of the first input signal relative to the transitioning of the first input signal in a manner such that the rate at which the second amplifier circuit generates the output signal increases as the first input signal transitions. - View Dependent Claims (17, 18, 19)
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20. A differential amplifier, comprising:
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a first amplifier having first and second differential transistors of a first type, the first differential transistor having a gate coupled to an input voltage node, and the second differential transistor having a gate coupled to a reference voltage node, one of the first and second differential transistors having a drain coupled to an output voltage node; and a second amplifier having third and fourth differential transistors of a second type that is different from the first type, the third differential transistor having a gate coupled to the input voltage node, and the fourth differential transistor having a gate coupled to the reference voltage node, one of the third and fourth differential transistors having a drain coupled to the output voltage node. - View Dependent Claims (21, 22, 23, 24)
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Specification