Method and system for independent I and Q loop amplitude control for quadrature generators

• US 8,036,316 B2
• Filed: 12/07/2009
• Issued: 10/11/2011
• Est. Priority Date: 12/06/2006
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Li, Qiang, Behzad, Arya, Roufoogaran, Razieh
• Primary Examiner(s): LUU, AN T
• Application Number:
  US12/632,184
• Publication Number:
  US 20100080325A1
• Time in Patent Office: 673 Days
• Field of Search: None
• US Class Current: 375/319
• CPC Class Codes: H04L 27/362 Modulation using more than one carrier, e.g. with quadrature carriers, separately amplitude modulated H04L27/366 takes precedence
• CPC Class Codes: H04L 27/364 Arrangements for overcoming imperfections in the modulator, e.g. quadrature error or unbalanced I and Q levels

Abstract

Certain aspects of a method and system for independent in-phase (I) and quadrature (Q) loop amplitude control for quadrature generators may include determining an amplitude voltage associated with an in-phase (I) component and a quadrature (Q) component of a generated signal. A DC reference voltage associated with the I component and the Q component may be determined. The determined amplitude voltage may be compared with the determined reference voltage to generate a control signal. The amplitude mismatch between the I component and the Q component may be compensated by controlling a biasing current of one or more programmable buffers associated with one or both of the I component and the Q component, based on the generated control signal.

Claims

1. A method for processing signals, the method comprising:

performing using one or more processors and/or circuits;

comparing an amplitude voltage and a DC reference voltage associated with an in-phase (I) component and a quadrature (Q) component of a signal;

adjusting said amplitude voltage associated with one or both of;

said I component and/or said Q component based on said comparison; and

controlling a programmable current source based on said comparison.

2. The method according to claim 1, comprising generating via said programmable current source, a biasing current, which is supplied to one or more programmable buffers.

3. The method according to claim 2, comprising individually controlling said biasing current of said one or more programmable buffers by adjusting a value of one or more bits.

4. A system for processing signals, the system comprising:

one or more processors and/or circuits that are operable to compare an amplitude voltage and a DC reference voltage associated with an in-phase (I) component and a quadrature (Q) component of a signal;

said one or more processors and/or circuits are operable to adjust said amplitude voltage associated with one or both of;

said I component and/or said Q component based on said comparison; and

said one or more processors and/or circuits comprise a programmable current source, and said one or more processors and/or circuits are operable to control said programmable current source based on said comparison.

5. The system according to claim 4, wherein said one or more processors and/or circuits are operable to generate via said programmable current source, a biasing current, which is supplied to one or more programmable buffers.

6. The system according to claim 5, wherein said one or more processors and/or circuits are operable to individually control said biasing current of said one or more programmable buffers by adjusting a value of one or more bits.

7. A machine-readable storage having stored thereon, a computer program having at least one code section for processing signals, the at least one code section being executable by a machine for causing the machine to perform steps comprising:

comparing an amplitude voltage and a DC reference voltage associated with an in-phase (I) component and a quadrature (Q) component of a signal;

adjusting said amplitude voltage associated with one or both of;

said I component and/or said Q component based on said comparison; and

controlling a programmable current source based on said comparison.

8. The machine-readable storage according to claim 7, wherein said at least one code section comprises code for generating via said programmable current source, a biasing current, which is supplied to one or more programmable buffers.

9. The machine-readable storage according to claim 8, wherein said at least one code section comprises code for individually controlling said biasing current of said one or more programmable buffers by adjusting a value of one or more bits.