Pulse receiving circuit, pulse receiving method and pulse wireless communication device

• US 8,036,320 B2
• Filed: 08/13/2008
• Issued: 10/11/2011
• Est. Priority Date: 08/20/2007
• Status: Active Grant

• Current Assignee: 138 East LCD Advancements Limited (Vector Capital Corporation)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Iida, Izumi
• Primary Examiner(s): Tran; Khanh C
• Application Number:
  US12/191,240
• Publication Number:
  US 20090052586A1
• Time in Patent Office: 1,154 Days
• Field of Search: 375/130, 375238-239, 375/259, 375/316, 375/340, 375/346, 370/212, 370/213, 329312-313
• US Class Current: 375/340
• CPC Class Codes: H04B 1/71637 Receiver aspects H04B1/7183 takes precedence
• CPC Class Codes: H04B 1/7174 Pulse generation in general H04L25/03834
• CPC Class Codes: H04L 25/4902 Pulse width modulation; Pulse position modulation
• CPC Class Codes: H04L 27/06 Demodulator circuits; Receiver circuits

Abstract

A pulse receiving circuit which receives a receiving signal from the outside includes: a template pulse generating circuit which generates a first pulse signal and a second pulse signal having phase different from that of the first pulse signal based on a pulse position timing signal; a first multiplying circuit which multiplies the receiving signal by the first pulse signal and outputs a first multiplication signal; a second multiplying circuit which multiplies the receiving signal by the second pulse signal and outputs a second multiplication signal; a first low band pass filtering circuit which extracts low frequency component from frequency components of the first multiplication signal and outputs a first low frequency signal; a second low band pass filtering circuit which extracts low frequency component from frequency components of the second multiplication signal and outputs a second low frequency signal; and an envelope detection circuit which performs envelope calculation by using the first low frequency signal and the second low frequency signal and outputs a detection signal.

Claims

1. A pulse receiving circuit which receives a receiving signal from the outside, comprising:

a template pulse generating circuit which generates a first pulse signal and a second pulse signal having phase different from that of the first pulse signal based on a pulse position timing signal;

a first multiplying circuit which multiplies the receiving signal by the first pulse signal and outputs a first multiplication signal;

a second multiplying circuit which multiplies the receiving signal by the second pulse signal and outputs a second multiplication signal;

a first low band pass filtering circuit which extracts low frequency component from frequency components of the first multiplication signal and outputs a first low frequency signal;

a second low band pass filtering circuit which extracts low frequency component from frequency components of the second multiplication signal and outputs a second low frequency signal; and

an envelope detection circuit which performs envelope calculation by using the first low frequency signal and the second low frequency signal and outputs a detection signal.

2. The pulse receiving circuit according to claim 1, wherein the phase difference between the first pulse signal and the second pulse signal is approximately 90 degrees.

3. The pulse receiving circuit according to claim 1, wherein the envelope detection circuit contains a half-wave rectifying circuit.

4. The pulse receiving circuit according to claim 1, wherein the envelope detection circuit contains a full-wave rectifying circuit.

5. The pulse receiving circuit according to claim 1, wherein the envelope detection circuit contains a square circuit.

6. The pulse receiving circuit according to claim 1, wherein the template pulse generating circuit includes:

a first pulse generating circuit and a second pulse generating circuit, each of which contains a first pin, a second pin, n (n;

two or larger integer) delay elements connected in series with the first pin, and a logic circuit outputting a pulse signal through the second pin based on a signal inputted through the first pin and n output signals outputted from the n delay elements;

a timing input pin through which the pulse position timing signal is inputted;

a first delay element; and

a second delay element having longer delay time than that of the first delay element,

the input pins of the first delay element and second delay element being connected with the timing input pin,

the output pin of the first delay element being connected with the first pin of the first pulse generating circuit to output the first pulse signal through the second pin of the first pulse generating circuit, and

the output pin of the second delay element being connected with the first pin of the second pulse generating circuit to output the second pulse signal through the second pin of the second pulse generating circuit.

7. The pulse receiving circuit according to claim 1, wherein the template pulse generating circuit includes:

a timing input pin through which the pulse position timing signal is inputted;

a multi-phase oscillating circuit which generates the first pulse signal and the second pulse signal; and

an ON-OFF control circuit connected between the input pin and the multi-phase oscillating circuit to output an ON-OFF signal which is turned on when the pulse position timing signal is turned on, and turned off after a time period longer than a pulse width of the receiving signal elapses from the time when the ON-OFF signal is turned on,

the multi-phase oscillating circuit generating the first pulse signal and the second pulse signal based on the ON-OFF control signal.

8. The pulse receiving circuit according to claim 1, wherein the template pulse generating circuit includes:

a first frequency control pulse generating circuit and a second frequency control pulse generating circuit, each of which contains a first pin, a second pin, n (n;

two or larger integer) delay control elements connected in series with the first pin and capable of controlling delay time based on a frequency control signal, and a logic circuit outputting a pulse signal through the second pin based on a signal inputted through the first pin and n output signals outputted from the n delay elements;

a timing input pin through which the pulse position timing signal is inputted;

a first delay element;

a second delay element having longer delay time than that of the first delay element; and

a frequency control circuit which outputs the frequency control signal,

input pins of the first delay element and the second delay element being connected with the timing input pin,

the output pin of the first delay element being connected with the first pin of the first frequency control pulse generating circuit to output the first pulse signal through the second pin of the first frequency control pulse generating circuit, and

the output pin of the second delay element being connected with the first pin of the second frequency control pulse generating circuit to output the second pulse signal through the second pin of the second frequency control pulse generating circuit.

9. The pulse receiving circuit according to claim 1, wherein the template pulse generating circuit includes:

a timing input pin through which the pulse position timing signal is inputted;

a frequency control multi-phase oscillating circuit which controls frequency of an oscillation signal based on a frequency control signal for generating the first pulse signal and the second pulse signal;

an ON-OFF control circuit connected between the input pin and the frequency control multi-phase oscillating circuit to output an ON-OFF signal which is turned on when the pulse position timing signal is turned on, and turned off after a time period longer than a pulse width of the receiving signal elapses from the time when the ON-OFF signal is turned on; and

a frequency control circuit which generates the frequency control signal based on the oscillation signal.

10. The pulse receiving circuit according to claim 1, wherein the template pulse generating circuit includes:

a first frequency control pulse generating circuit and a second frequency control pulse generating circuit, each of which contains a first pin, a second pin, n (n;

two or larger integer) delay control elements connected in series with the first pin and capable of controlling delay time based on a frequency control signal, and a logic circuit outputting a pulse signal through the second pin based on a signal inputted through the first pin and n output signals outputted from the n delay elements;

a frequency control circuit which contains a ring oscillating circuit having m (m;

2 or larger integer) delay control elements having delay characteristics substantially equivalent or proportional to those of the delay control elements and outputs the frequency control signal based on an output signal from the ring oscillating circuit;

a timing input pin through which the pulse position timing signal is inputted;

a first delay element;

a second delay element having longer delay time than that of the first delay element; and

input pins of the first delay element and the second delay element being connected with the timing input pin,

the output pin of the first delay element being connected with the first pin of the first frequency control pulse generating circuit to output the first pulse signal through the second pin of the first frequency control pulse generating circuit, and

the output pin of the second delay element being connected with the first pin of the second frequency control pulse generating circuit to output the second pulse signal through the second pin of the second frequency control pulse generating circuit.

11. The pulse receiving circuit according to claim 1, wherein the template pulse generating circuit includes:

a first frequency control pulse generating circuit and a second frequency control pulse generating circuit, each of which contains a first pin, a second pin, n (n;

two or larger integer) delay control elements connected in series with the first pin and capable of controlling delay time based on a frequency control signal, and a logic circuit outputting a pulse signal through the second pin based on a signal inputted through the first pin and n output signals outputted from the n delay elements;

a frequency control circuit which contains a ring oscillating circuit having m (m;

2 or larger integer) delay elements having delay characteristics substantially equivalent or proportional to those of the delay control elements, a counter circuit which counts an output signal from the ring oscillating circuit and outputs a count value, and a ROM table which stores the value of the frequency control signal corresponding to the count value;

a timing input pin through which the pulse position timing signal is inputted;

a first delay element;

a second delay element having longer delay time than that of the first delay element; and

input pins of the first delay element and the second delay element being connected with the timing input pin,

the output pin of the first delay element being connected with the first pin of the first frequency control pulse generating circuit to output the first pulse signal through the second pin of the first frequency control pulse generating circuit, and

the output pin of the second delay element being connected with the first pin of the second frequency control pulse generating circuit to output the second pulse signal through the second pin of the second frequency control pulse generating circuit.

12. A pulse receiving circuit, comprising:

a first pulse receiving circuit which contains the pulse receiving circuit according to claim 1;

a second pulse receiving circuit which contains a half-wave rectifying detection circuit; and

a communication path quality judging circuit which judges quality of a communication path;

wherein

the receiving signal is inputted to the first pulse receiving circuit to output the detection signal when the quality of the communication path is lower than predetermined quality, and

the receiving signal is inputted to the second pulse receiving circuit to output the detection signal when the quality of the communication path is higher than the predetermined quality.

13. A pulse receiving circuit, comprising:

a first pulse receiving circuit which contains the pulse receiving circuit according to claim 1;

a second pulse receiving circuit which contains a full-wave rectifying detection circuit; and

a communication path quality judging circuit which judges quality of a communication path,

wherein

the receiving signal is inputted to the first pulse receiving circuit to output the detection signal when the quality of the communication path is lower than predetermined quality, and

the receiving signal is inputted to the second pulse receiving circuit to output the detection signal when the quality of the communication path is higher than the predetermined quality.

14. A pulse receiving circuit, comprising:

a first pulse receiving circuit which contains the pulse receiving circuit according to claim 1;

a second pulse receiving circuit which contains a square detection circuit; and

a communication path quality judging circuit which judges quality of a communication path,

wherein

the receiving signal is inputted to the first pulse receiving circuit to output the detection signal from the first pulse receiving circuit when the quality of the communication path is lower than predetermined quality, and

the receiving signal is inputted to the second pulse receiving circuit to output the detection signal from the second pulse receiving circuit when the quality of the communication path is higher than the predetermined quality.

15. A pulse receiving circuit, comprising:

a first pulse receiving circuit which contains the pulse receiving circuit according to claim 1;

a second pulse receiving circuit which contains a synchronous detection circuit; and

a communication path quality judging circuit which judges quality of a communication path,

wherein

the receiving signal is inputted to the second pulse receiving circuit to output the detection signal from the second pulse receiving circuit when the quality of the communication path is lower than predetermined quality, and

the receiving signal is inputted to the first pulse receiving circuit to output the detection signal from the first pulse receiving circuit when the quality of the communication path is higher than the predetermined quality.

16. A pulse receiving circuit, comprising:

a first pulse receiving circuit which contains the pulse receiving circuit according to claim 1;

a second pulse receiving circuit which contains a synchronous detection circuit;

a communication path quality judging circuit which judges quality of a communication path; and

a phase control circuit which outputs the pulse position timing signal based on a clock signal,

wherein

the clock signal is produced by a resonance oscillator and the receiving signal is inputted to the second pulse receiving circuit to output the detection signal from the second pulse receiving circuit when the quality of the communication path is lower than predetermined quality, and

the clock signal is produced by a ring oscillator and the receiving signal is inputted to the first pulse receiving circuit to output the detection signal from the first pulse receiving circuit when the quality of the communication path is higher than the predetermined quality.

17. A pulse receiving circuit, comprising:

a first pulse receiving circuit which contains the pulse receiving circuit according to claim 1;

a second pulse receiving circuit which contains a synchronous detection circuit;

a third pulse receiving circuit as an envelope detection circuit; and

a communication path quality judging circuit which judges quality of a communication path,

wherein

the receiving signal is inputted to the second pulse receiving circuit to output the detection signal from the second pulse receiving circuit when the quality of the communication path is lower than first quality as predetermined quality,

the receiving signal is inputted to the first pulse receiving circuit to output the detection signal from the first pulse receiving circuit when the quality of the communication path lies within the range between the first quality and second quality higher than the first quality, and

the receiving signal is inputted to the third pulse receiving circuit to output the detection signal from the third pulse receiving circuit when the quality of the communication path is higher than the second quality.

18. A pulse receiving circuit, comprising:

a first pulse receiving circuit which contains the pulse receiving circuit according to claim 1;

a second pulse receiving circuit which contains a synchronous detection circuit;

a variable ring oscillating circuit which has p+q (p,q;

arbitrary natural numbers) delay elements and switches between ring oscillation using the p delay elements and ring oscillation using the p+q delay elements; and

a phase control circuit which outputs the pulse position timing signal based on a clock signal,

wherein

the ring oscillation of the variable ring oscillating circuit using the p delay elements is selected and the receiving signal is inputted to the second pulse receiving circuit to output the detection signal from the second pulse receiving circuit when generation of the receiving signal is more frequent than a predetermined value, and

the ring oscillation of the variable ring oscillating circuit using the p+q delay elements is selected and the receiving signal is inputted to the first pulse receiving circuit to output the detection signal from the first pulse receiving circuit when generation of the receiving signal is more frequent than a predetermined value.

19. A pulse wireless communication device includes:

the pulse receiving circuit according to claim 1; and

a pulse transmitting circuit.

20. A pulse receiving method of receiving a signal from the outside comprising:

generating a first pulse signal based on a pulse position timing signal;

multiplying the receiving signal by the first pulse signal;

outputting a first multiplication signal;

extracting low frequency component from frequency components of the first multiplication signal;

outputting a first low frequency signal;

generating a second pulse signal having phase different from that of the first pulse signal based on the pulse position timing signal;

multiplying the receiving signal by the second pulse signal;

outputting a second multiplication signal;

extracting low frequency component from frequency components of the second multiplication signal;

outputting a second low frequency signal;

performing envelope calculation by using the first low frequency signal and the second low frequency signal; and

outputting a detection signal based on the result of envelope calculation.