Variable impedance sense architecture and method

• US 8,036,846 B1
• Filed: 09/28/2006
• Issued: 10/11/2011
• Est. Priority Date: 10/20/2005
• Status: Expired due to Fees

• Current Assignee: RPX Corporation
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Vullaganti, Kalyana C.
• Primary Examiner(s): Kundu, Sujoy K
• Application Number:
  US11/540,996
• Time in Patent Office: 1,839 Days
• Field of Search: 702/104, 702/107, 702/110, 702/57, 702/64, 702/65, 702/100, 326/21, 326/30, 326/121, 324/158.1, 324/763, 324/600, 324/601, 324/629, 324/649, 324/691, 327/100, 327/524, 327/568, 327/588, 374/100, 374/101, 374/137, 374/141, 374/142, 377/1, 377 13- 16, 377/19
• US Class Current: 702/104
• CPC Class Codes: H03K 19/0005 Modifications of input or output impedance

Abstract

A variable impedance sense (VIS) circuit (400) can detect a drift in the impedance of variable impedance circuits due to changes in operating conditions. Adjustments to binary impedance setting codes are made in response to a detected drift only when such changes do not increase a worst case variation from a target impedance. Adjustments can also be made in response to a detected input offset polarity.

Claims

1. A variable impedance sense circuit, comprising:

a comparator having inputs coupled to at least a first array of switchable impedance elements, the comparator outputting a first drift value that indicates a detected change in the impedance of the first array; and

at least a first counter circuit that generates a count value for calibrating the first array, the at least first counter circuit modifying the count value in response to the first drift value when such a modification does not increase an impedance difference between the first array and a reference impedance to generate an output count value.

2. The variable impedance sense circuit of claim 1, wherein:

the at least first counter circuit increases an initial count value in response to the drift value having a first value to generate a drift down compensated count, and decreases the initial count value in response to the drift value having a second value to generate a drift up compensated count.

3. The variable impedance sense circuit of claim 2, wherein:

the comparator outputs a second drift value in response to the first drift value; and

the at least first counter circuit

decrements a drift down compensated count if an input offset of the comparator has a first offset value and the second drift value is different from the first drift value, and

increments a drift up compensated count value if an input offset of the comparator has a second offset value and the second drift value is different from the first drift value.

4. The variable impedance sense circuit of claim 1, wherein:

the comparator outputs an offset value in response to a same reference value being applied to both comparator inputs; and

the at least first counter circuit generates a multi-bit initial count value and increments the initial count value in response to the offset value having a first value and a least significant bit (LSB) of one, and increments the initial count value in response to the offset value having a second value.

5. The variable impedance sense circuit of claim 1, wherein:

the at least first counter circuit comprises a successive approximation register that sequentially sets bit values of the initial binary value according to output values from the comparator, starting with a most significant bit and ending with a least significant bit.

6. The variable impedance sense circuit of claim 1, wherein:

the first array of variable switchable impedance elements comprises a pull-up array coupled between a calibration node and a high power supply node and coupled to receive the output count value.

7. The variable impedance sense circuit of claim 1, wherein:

the count value is a binary value; and

the at least first counter circuit increments the count value to generate the output count value when the drift value has one value, the at least first counter circuit decrements the count value to generate the output count value when the drift value has another value.

8. The variable impedance sense circuit of claim 1, further including:

the comparator has a first input and a second input; and

a switch circuit having a first switch element that provides a controllable path between the comparator first input and a reference voltage and a second switch element that provides a controllable path between the comparator second input and the reference voltage.

9. The variable impedance sense circuit of claim 1, wherein:

the at least first counter circuit includes

a counter that outputs count values and modified count values,

a first update register that stores count values,

a second update register that stores modified count values, and

a multiplexer having one input coupled to the first update register and another input coupled to the second update register.

10. A method of sensing an impedance value for input/output (I/O) matching that compensates for drifts in variable impedance elements, comprising the steps of:

detecting a first drift change in variable impedance elements;

generating a multi-bit digital value corresponding to a reference impedance with an analog-to-digital conversion; and

adjusting the digital value according to the first drift change in the variable impedance elements when such an adjustment does not increase an impedance difference between the variable impedance elements and the reference impedance.

11. The method of claim 10, wherein:

detecting the first drift change includes applying a reference voltage to one input of a comparator and coupling another input of the comparator to a voltage divider circuit including the reference impedance and the variable impedance elements.

12. The method of claim 10, wherein:

adjusting the digital value includes,

if an offset voltage at an input of the comparator has a first polarity and the LSB is one, incrementing the digital value by one, and

if the offset voltage has a second polarity incrementing the digital value by one.

13. The method of claim 12, further including:

generating a drift compensation value, comprising

if the drift change is in a first direction, incrementing the digital value by one to generate a drift down compensated value, and

if the drift change is in a second direction, decrementing the digital value by one to generate a drift up compensated value.

14. The method of claim 13, further including:

if the offset voltage has the first polarity,

applying any drift down compensated value to the variable impedance elements to detect a second drift change, and

decrementing the drift down compensated value if the second drift change is in a different direction than the first drift change with respect to the reference impedance.

15. The method of claim 13, wherein:

if the offset voltage has the second polarity,

applying any drift up compensated value to the variable impedance elements to detect a second drift change, and

incrementing the drift up compensated value if the second drift change is in a different direction than the first drift change with respect to the reference impedance.

16. The method of claim 14, further including:

if the offset voltage has the first polarity and the least significant bit (LSB) of the adjusted count value is one, incrementing the adjusted count value by one.

17. A variable impedance sensing architecture, comprising:

an analog-to-digital converter (ADC) circuit having inputs coupled to a first variable impedance array and a second variable impedance array that outputs a drift indication reflecting a change in at least one of the variable impedance arrays and an input offset indication; and

a counter/control circuit that selectively adjusts a binary code representing an impedance of at least one of the variable impedance arrays in response to at least the drift indication value and the input offset indication.

18. The variable impedance sensing architecture of claim 17, wherein:

the counter/control circuit adjusts the binary code in response to the drift indication and offset indication having one set of values and does not adjust the binary code in response to the drift indication and offset indication having another set of values.

19. The variable impedance sensing architecture of claim 17, wherein:

the ADC circuit is a successive approximation register (SAR) type ADC comprising, a comparator having inputs coupled to the first variable impedance array and second variable impedance array, and an output coupled to a SAR register.

20. The variable impedance sensing architecture of claim 17, wherein:

the counter/control circuit comprises

a successive approximation register (SAR) store comprising a counter,

a first update register coupled to the SAR store to receive the binary code, and

a second update register coupled to the SAR store to receive the updated binary code.

21. The variable impedance sensing architecture of claim 17, wherein:

the counter/control circuit selectively adjusts a first binary code representing an impedance of a pull-up variable impedance array in response to at least the drift indication value and the input offset indication, and selectively adjusts a second binary code representing an impedance of a pull-down variable impedance array in response to at least the drift indication value and the input offset indication.