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Bridge device with page-access based processor interface

  • US 8,037,228 B2
  • Filed: 08/14/2008
  • Issued: 10/11/2011
  • Est. Priority Date: 08/24/2007
  • Status: Active Grant
First Claim
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1. An integrated circuit bridge device, comprising:

  • a first page-access (PA) processor interface circuit coupled to a buffer circuit and configurable in response to configuration information to receive command information, address information, and data values on a same multi-bit input/output (I/O) bus;

    a second page-access (PA) processor interface circuit coupled to the buffer circuit and configured to communicate according to a first communication protocol different from that executable by the first interface circuit; and

    a controller circuit formed in the same substrate as the first and second interface circuits, the controller circuit configured to enable data transfers between the first interface circuit and the second interface circuits via the buffer circuit.

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