Bridge device with page-access based processor interface
First Claim
1. An integrated circuit bridge device, comprising:
- a first page-access (PA) processor interface circuit coupled to a buffer circuit and configurable in response to configuration information to receive command information, address information, and data values on a same multi-bit input/output (I/O) bus;
a second page-access (PA) processor interface circuit coupled to the buffer circuit and configured to communicate according to a first communication protocol different from that executable by the first interface circuit; and
a controller circuit formed in the same substrate as the first and second interface circuits, the controller circuit configured to enable data transfers between the first interface circuit and the second interface circuits via the buffer circuit.
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Accused Products
Abstract
An integrated circuit bridge device can include a first interface circuit coupled to a buffer circuit and a configurable in response to configuration information to receive command information, address information, and data values on a same multi-bit input/output (I/O) bus. A second interface circuit can be coupled to the buffer circuit and configured to communicate according to a first communication protocol different from that executable by the first interface circuit. In addition, a controller circuit formed in the same substrate as the first and second interface circuits can be configured to enable data transfers between the first interface circuit and the second interface circuits via the buffer circuit.
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Citations
20 Claims
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1. An integrated circuit bridge device, comprising:
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a first page-access (PA) processor interface circuit coupled to a buffer circuit and configurable in response to configuration information to receive command information, address information, and data values on a same multi-bit input/output (I/O) bus; a second page-access (PA) processor interface circuit coupled to the buffer circuit and configured to communicate according to a first communication protocol different from that executable by the first interface circuit; and a controller circuit formed in the same substrate as the first and second interface circuits, the controller circuit configured to enable data transfers between the first interface circuit and the second interface circuits via the buffer circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A bridge device, comprising:
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a page-access (PA) processor interface having a plurality of processor input/outputs (I/Os) for receiving processor commands, addresses and data on a same set of I/Os; a buffer circuit having a plurality of storage locations logically dividable into a plurality of endpoints; and a controller circuit comprising a processor and an instruction memory configurable to assign endpoints of the buffer circuit to at least a host interface having host inputs/outputs (I/Os) configured to receive data in a predetermined packet format, or to a storage interface having storage I/Os configurable to access data from a storage device, and to enable a data transfer path between the processor interface and a predetermined endpoint based on at least address information received on the processor I/Os. - View Dependent Claims (12, 13, 14)
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15. A method of enabling a page-access based processor to access non-page-access based devices, comprising the steps of:
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(a) associating buffer locations with one of at least a second interface and a third interface of the same integrated circuit device; and (b) in response to a predetermined sequence of command data and address data received on a same set of input/output (I/O) lines at a first interface of the integrated device, coupling the I/O lines to one of the buffer locations. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification