Command queuing smart storage transfer manager for striping data to raw-NAND flash modules
First Claim
1. A multi-level flash device comprising:
- a smart storage switch which comprises;
an upstream interface to a host for receiving host commands to access non-volatile memory (NVM) and for receiving host data and a host address;
a smart storage transaction manager that manages transactions from the host;
a virtual storage processor that maps the host address to an assigned flash module to generate a logical block address (LBA), the virtual storage processor performing a first level of mapping;
a virtual storage bridge between the smart storage transaction manager and a LBA bus;
a NVM controller, coupled to the LBA bus to receive the LBA generated by the virtual storage processor and the host data from the virtual storage bridge;
a second-level mapper, in the NVM controller, that maps the LBA to a physical block address (PBA);
a plurality of flash modules that include the assigned flash module, wherein a flash module comprises;
raw-NAND flash memory chips, coupled to the NVM controller, for storing the host data at a block location identified by the PBA generated by the second-level mapper in the NVM controller;
a volatile memory buffer for temporarily storing the host data in a volatile memory that loses data when power is disconnected;
wherein the raw-NAND flash memory chips in the plurality of flash module are non-volatile memory that retain data when power is disconnected;
wherein the smart storage switch further comprises;
a virtual buffer bridge, coupled between the smart storage transaction manager and the volatile memory buffer;
a sector data buffer, in the volatile memory buffer, for temporarily caching the host data, the sector data buffer having L locations for storing the host data;
a Q-R pointer table, in the volatile memory buffer, for storing a quotient Q and a remainder R generated by division of a host address by L;
wherein Q, R, and L are whole numbers;
wherein R identifies one of the L locations in the sector data buffer,whereby address mapping is performed at two levels to access the raw-NAND flash memory chips.
2 Assignments
0 Petitions
Accused Products
Abstract
A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands.
79 Citations
16 Claims
-
1. A multi-level flash device comprising:
-
a smart storage switch which comprises; an upstream interface to a host for receiving host commands to access non-volatile memory (NVM) and for receiving host data and a host address; a smart storage transaction manager that manages transactions from the host; a virtual storage processor that maps the host address to an assigned flash module to generate a logical block address (LBA), the virtual storage processor performing a first level of mapping; a virtual storage bridge between the smart storage transaction manager and a LBA bus; a NVM controller, coupled to the LBA bus to receive the LBA generated by the virtual storage processor and the host data from the virtual storage bridge; a second-level mapper, in the NVM controller, that maps the LBA to a physical block address (PBA); a plurality of flash modules that include the assigned flash module, wherein a flash module comprises; raw-NAND flash memory chips, coupled to the NVM controller, for storing the host data at a block location identified by the PBA generated by the second-level mapper in the NVM controller; a volatile memory buffer for temporarily storing the host data in a volatile memory that loses data when power is disconnected; wherein the raw-NAND flash memory chips in the plurality of flash module are non-volatile memory that retain data when power is disconnected; wherein the smart storage switch further comprises; a virtual buffer bridge, coupled between the smart storage transaction manager and the volatile memory buffer; a sector data buffer, in the volatile memory buffer, for temporarily caching the host data, the sector data buffer having L locations for storing the host data; a Q-R pointer table, in the volatile memory buffer, for storing a quotient Q and a remainder R generated by division of a host address by L; wherein Q, R, and L are whole numbers; wherein R identifies one of the L locations in the sector data buffer, whereby address mapping is performed at two levels to access the raw-NAND flash memory chips. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A solid-state disk comprising:
-
volatile memory buffer means for temporarily storing host data in a volatile memory that loses data when power is disconnected; smart storage switch means for switching host commands to a plurality of downstream devices, the smart storage switch means comprising; upstream interface means, coupled to a host, for receiving host commands to access flash memory and for receiving host data and a host address; smart storage transaction manager means for managing transactions from the host; virtual storage processor means for translating the host address to an assigned flash module to generate a logical block address (LBA), the virtual storage processor means performing a first level of mapping; virtual storage bridge means for transferring host data and the LBA between the smart storage transaction manager means and a LBA bus; data striping means for dividing the host data into data segments that are assigned to different ones of the plurality of flash modules; a plurality of flash modules that include the assigned flash module, wherein a flash module comprises; lower-level controller means for controlling flash operations, coupled to the LBA bus to receive the LBA generated by the virtual storage processor means and the host data from the virtual storage bridge means; second-level map means, in the lower-level controller means, for mapping the LBA to a physical block address (PBA); and raw-NAND flash memory chips, coupled to the lower-level controller means, for storing the host data at a block location identified by the PBA generated by the second-level map means in the lower-level controller means; wherein the raw-NAND flash memory chips in the plurality of flash modules are non-volatile memory that retain data when power is disconnected; sector data buffer means, in the volatile memory buffer means, for storing host data, the sector data buffer means having L locations for storing host data; command queue means, in the volatile memory buffer means, for storing entries for commands received from the host that have not yet written data to the raw-NAND flash memory chips; and Q-R pointer table means, in the volatile memory buffer means, for storing a quotient Q and a remainder R generated by division of a host address by L; wherein Q, R, and L are whole numbers; wherein R identifies one of the L locations in the sector data buffer means, whereby address mapping is performed at two levels to access the raw-NAND flash memory chips. - View Dependent Claims (10)
-
-
11. A solid-state disk comprising:
-
volatile memory buffer means for temporarily storing host data in a volatile memory that loses data when power is disconnected; smart storage switch means for switching host commands to a plurality of downstream devices, the smart storage switch means comprising; upstream interface means, coupled to a host, for receiving host commands to access flash memory and for receiving host data and a host address; smart storage transaction manager means for managing transactions from the host; virtual storage processor means for translating the host address to an assigned flash module to generate a logical block address (LBA), the virtual storage processor means performing a first level of mapping; virtual storage bridge means for transferring host data and the LBA between the smart storage transaction manager means and a LBA bus; data striping means for dividing the host data into data segments that are assigned to different ones of the plurality of flash modules; a plurality of flash modules that include the assigned flash module, wherein a flash module comprises; lower-level controller means for controlling flash operations, coupled to the LBA bus to receive the LBA generated by the virtual storage processor means and the host data from the virtual storage bridge means; second-level map means, in the lower-level controller means, for mapping the LBA to a physical block address (PBA); and raw-NAND flash memory chips, coupled to the lower-level controller means, for storing the host data at a block location identified by the PBA generated by the second-level map means in the lower-level controller means; wherein the raw-NAND flash memory chips in the plurality of flash modules are non-volatile memory that retain data when power is disconnected; wherein the raw-NAND flash memory chips comprise two flash die that are stacked together and accessible by interleaving, and wherein each of the two flash die comprises two planes that are accessible by interleaving; wherein a size of a data segment is equal to four pages per channel, and each channel has one of the plurality of flash modules, whereby the host data is striped with a depth to match the plurality of flash modules, whereby address mapping is performed at two levels to access the raw-NAND flash memory chips. - View Dependent Claims (12, 13)
-
-
14. A striping non-volatile-memory (NVM) system comprising:
-
an upstream interface to a host that generates host data and host commands in a host sequence of commands; a smart storage transaction manager, coupled to the upstream interface, for re-ordering the host commands from the host sequence into a reordered sequence of operations; a plurality of NVM modules each having a plurality of NVM memory blocks for storing the host data in non-volatile solid-state memory that retains data when power is disconnected; a virtual storage processor that assigns host commands to an assigned device in the plurality of NVM modules, the virtual storage processor also storing attributes obtained from each of the plurality of NVM modules, the attributes including memory capacities, wherein the virtual storage processor reports an aggregate sum of the memory capacities to the host; a data striping unit for segmenting host data into data segments stored on several of the plurality of NVM modules; a virtual storage bridge, coupled between the smart storage transaction manager and the plurality of NVM modules; a lower-level controller for each of the plurality of NVM modules, the lower-level controller comprising; a remapping unit for converting logical addresses received from the virtual storage bridge into physical addresses for accessing the plurality of NVM memory blocks in the NVM module; a dynamic-random-access memory (DRAM) buffer for temporarily storing the host data; a virtual buffer bridge between the DRAM buffer and the smart storage transaction manager, a sector data buffer, in the DRAM buffer, for temporarily caching the host data, the sector data buffer having L locations for storing the host data; a Q-R pointer table, in the DRAM buffer, for storing a quotient Q and a remainder R generated by division of a host address by L; wherein Q, R, and L are whole numbers; wherein R identifies one of the L locations in the sector data buffer, whereby high-level data striping is performed before the host data is sent to the plurality of NVM modules. - View Dependent Claims (15, 16)
-
Specification