Vertical gated access transistor

• US 8,039,348 B2
• Filed: 05/24/2010
• Issued: 10/18/2011
• Est. Priority Date: 03/02/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengling, Werner
• Primary Examiner(s): Ghyka; Alexander
• Application Number:
  US12/785,712
• Publication Number:
  US 20100230733A1
• Time in Patent Office: 512 Days
• Field of Search: 438/270, 438/669
• US Class Current: 438/270
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/36 the transistor being a FinFET

Abstract

According to one embodiment of the present invention, a method of forming an apparatus comprises forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At least one of the shallow trenches is positioned between two deep trenches. The plurality of shallow trenches and the plurality of deep trenches are parallel to each other. The method further comprises depositing a layer of conductive material over the first region and a second region of the substrate. The method further comprises etching the layer of conductive material to define a plurality of lines separated by a plurality of gaps over the first region of the substrate, and a plurality of active device elements over the second region of the substrate. The method further comprises masking the second region of the substrate. The method further comprises removing the plurality of lines from the first region of the substrate, thereby creating a plurality of exposed areas from which the plurality of lines were removed. The method further comprises etching a plurality of elongate trenches in the plurality of exposed areas while the second region of the substrate is masked.

Claims

1. A method of forming an integrated circuit, the method comprising:

forming a plurality of U-shaped semiconductor structures in a first region of a substrate;

depositing a layer of conductive material over the first region and a second region of the substrate;

etching a pattern into the layer of conductive material over the first region of the substrate, wherein etching the pattern further comprises forming a plurality of active device elements from the layer of conductive material over the second region of the substrate;

protectively masking the second region of the substrate to protect the layer of conductive material in the second region; and

etching a plurality of trenches in the first region using the pattern of the layer of conductive material in the first region as an etch mask while the second region of the substrate is protectively masked.

2. The method of claim 1, wherein the pattern comprises a plurality of lines separated by a plurality of gaps and the plurality of trenches comprises elongate trenches following the pattern.

3. The method of claim 2, further comprising, after etching the pattern, filling the gaps with a hard mask material and removing the plurality of lines from the first region of the substrate, thereby creating a plurality of exposed areas from which the plurality of lines were removed, wherein etching the plurality of trenches in the first region using the pattern comprises etching the substrate in the exposed areas.

4. The method of claim 2, wherein the U-shaped semiconductor structures in the first region are defined by a plurality of deep trenches and a plurality of shallow trenches, and the elongate trenches cross the plurality of deep trenches and the plurality of shallow trenches.

5. The method of claim 4, wherein the elongate trenches have an intermediate depth between depths of the deep trenches and the shallow trenches.

6. The method of claim 1, wherein the layer of conductive material comprises a layer of polycrystalline silicon and a layer of metallic material.

7. The method of claim 1, further comprising:

depositing an insulating material over the first region and the second region of the substrate after etching the plurality of elongate trenches;

planarizing the insulating material to expose the conductive material in the second region;

depositing a metal layer over the substrate, such that the metal layer contacts the exposed conductive material in the second region; and

creating a silicide region of the conductive material.

8. The method of claim 1, further comprising forming a plurality of elongate sidewall spacers in the plurality of trenches, wherein the elongate sidewall spacers comprise gate electrode material.

9. The method of claim 1, wherein the plurality of deep trenches and the plurality of shallow trenches are formed before the plurality of elongate trenches are etched.

10. The method of claim 1, wherein the active device elements in the second region are transistor gate stacks each having an oxide layer and a polycrystalline silicon region without an insulating cap formed thereover.