Structure and method for forming hybrid substrate

• US 8,039,401 B2
• Filed: 12/10/2008
• Issued: 10/18/2011
• Est. Priority Date: 12/14/2007
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Sharp, Joelle, Chen, Hui, Wang, Qi, Li, Minhua
• Primary Examiner(s): Ghyka; Alexander
• Assistant Examiner(s): NIKMANESH, SEAHVOSH J
• Application Number:
  US12/332,326
• Publication Number:
  US 20090302482A1
• Time in Patent Office: 1,042 Days
• Field of Search: 438/455, 438/478, 438/694, 438/700, 257/E21.088, 257/E21.567, 257/E21.214, 257/E21.599
• US Class Current: 438/700
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02609 Crystal orientation
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/02642 Mask materials other than SiO2 or SiN
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A first and a second substrate are bonded together to thereby form a unitary hybrid substrate. Predefined portions of the first substrate are removed to form openings in the first substrate through which surface regions of the second substrate are exposed. A selective epitaxial growth process that is selective with respect to the crystalline orientations of the first and second substrates is carried out to thereby form epitaxial silicon from the exposed surfaces of the second substrate but not from exposed surfaces of the first substrate. The epitaxial silicon formed from the exposed surfaces of the second substrate has the same crystalline orientation as the second substrate.

Claims

1. A method for forming a hybrid substrate, comprising:

providing first and second substrates having different crystalline orientations;

bonding the first and second substrates together to thereby form a unitary hybrid substrate;

removing predefined portions of the first substrate to form openings in the first substrate through which surface regions of the second substrate are exposed; and

carrying out a selective epitaxial growth process that is selective with respect to the crystalline orientations of the first and second substrates to thereby form epitaxial silicon from the exposed surfaces of the second substrate but not from exposed surfaces of the first substrate, wherein the epitaxial silicon formed from the exposed surfaces of the second substrate has the same crystalline orientation as the second substrate;

wherein the selective epitaxial growth process comprises a chlorine-containing etchant that provides a faster etch rate of the epi along the exposed surfaces of the first substrate than the epi along the exposed surfaces of the second substrate.

2. The method of claim 1 further comprising:

prior to the bonding step, forming a hydrogen-rich region at a predetermined depth within the first substrate; and

after the bonding step, performing a cleaving process to separate the first substrate into two portions along the hydrogen-rich region.

3. The method of claim 1, wherein prior to the removing step the first substrate is thinned down to a desired thickness.

4. The method of claim 1 further comprising:

forming first and second transistors in the epitaxial silicon and the second substrate, respectively, the first transistor being capable of operating based on hole current conduction, and the second transistor being capable of operating based on electron current conductions.

5. The method of claim 1 further comprising:

performing a silicon removal process so that a top surface of the second substrate and a top surface of the epitaxial silicon become substantially coplanar.

6. The method of claim 1, wherein the grown epitaxial silicon directly contacts sidewalls of the openings in the first substrate.

7. The method of claim 1 further comprising:

prior to forming the epitaxial silicon, forming dielectric spacers along sidewalls of the openings in the first substrate so that after the epitaxial silicon is formed, the dielectric spacers insulate the epitaxial silicon from the first substrate.

8. The method of claim 1, wherein the selective epitaxial growth process provides a faster growth rate along the exposed surfaces of the second substrate than along the exposed surfaces of the first substrate.

9. The method of claim 1, further comprising forming a P-channel trench gate power MOSFET in the first substrate and an N-channel trench gate power MOSFET in the epitaxial silicon formed by the selective epitaxial growth process over the second substrate.

10. The method of claim 1, further comprising forming a P-channel shielded gate power MOSFET in the first substrate and an N-channel shielded gate power MOSFET in the epitaxial silicon formed by the selective epitaxial growth process over the second substrate.

11. A method for forming a hybrid substrate, comprising:

providing first and second substrates having different crystalline orientations;

bonding the first and second substrates together to thereby form a unitary hybrid substrate;

removing predefined portions of the first substrate to form openings in the first substrate through which surface regions of the second substrate are exposed; and

carrying out a selective epitaxial growth process that is selective with respect to the crystalline orientations of the first and second substrates to thereby form epitaxial silicon from the exposed surfaces of the second substrate but not from exposed surfaces of the first substrate, wherein the epitaxial silicon formed from the exposed surfaces of the second substrate has the same crystalline orientation as the second substrate; and

forming a DC-DC converter having a PMOS transistor formed in the first substrate and an NMOS transistor formed in the epitaxial silicon formed by the selective epitaxial growth process over the second substrate.

12. The method of claim 11 further comprising:

providing a first substrate having a first dielectric layer extending over a surface of the first substrate, and a second substrate having a second dielectric layer extending over a surface of the second substrate, wherein the first and second dielectric layers together form the dielectric layer.

13. The method of claim 11 further comprising:

prior to the bonding step, forming a hydrogen-rich region at a predetermined depth within the first substrate; and

after the bonding step, performing a cleaving process to separate the first substrate into two portions along the hydrogen-rich region.

14. The method of claim 11, wherein prior to the removing step the first substrate is thinned down to a desired thickness.

15. The method of claim 11 further comprising:

forming first and second transistors in the epitaxial silicon and the second substrate, respectively, the first transistor being capable of operating based on hole current conduction, and the second transistor being capable of operating based on electron current conductions.

16. The method of claim 11 further comprising:

performing a silicon removal process so that a top surface of the second substrate and a top surface of the epitaxial silicon are substantially coplanar.

17. The method of claim 11, wherein the grown epitaxial silicon directly contacts sidewalls of the openings in the first substrate.

18. The method of claim 11 further comprising:

prior to forming the epitaxial silicon, forming dielectric spacers along sidewalls of the openings in the first substrate and the first and second dielectric layers so that after the epitaxial silicon is formed, the dielectric spacers insulate the epitaxial silicon from the first substrate.