Thin film transistor and display device including thin film transistor

• US 8,039,842 B2
• Filed: 05/15/2009
• Issued: 10/18/2011
• Est. Priority Date: 05/22/2008
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Jinbo, Yasuhiro
• Primary Examiner(s): Richards; N Drew
• Assistant Examiner(s): CARPENTER, ROBERT K
• Application Number:
  US12/467,048
• Publication Number:
  US 20090289256A1
• Time in Patent Office: 886 Days
• Field of Search: 257/57, 257/59, 257/E29.291, 257/E37.004, 257/E33.004
• US Class Current: 257/59
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A thin film transistor with favorable electric characteristics is provided, which includes a gate electrode layer; a first insulating layer covering the gate electrode layer; a pair of impurity semiconductor layers forming source and drain regions, which are provided with a distance therebetween and at least partly overlap with the gate electrode layer; a microcrystalline semiconductor layer which is provided over the first insulating layer in part of a channel formation region, and at least partly overlaps with the gate electrode layer and does not overlap with at least one of the pair of impurity semiconductor layers; a second insulating layer between and in contact with the first insulating layer and the microcrystalline semiconductor layer; and an amorphous semiconductor layer over the first insulating layer, covering the second insulating layer and the microcrystalline semiconductor layer. The first insulating layer is a silicon nitride layer and the second insulating layer is a silicon oxynitride layer.

Claims

1. A thin film transistor comprising:

a gate electrode layer;

a first insulating layer which is provided so as to cover the gate electrode layer;

a pair of impurity semiconductor layers forming a source region and a drain region, which are provided with a distance therebetween and which at least partly overlap with the gate electrode layer;

a microcrystalline semiconductor layer which is provided over the first insulating layer in part of a channel formation region and which at least partly overlaps with the gate electrode layer and does not overlap with the pair of impurity semiconductor layers;

a second insulating layer which is provided between and in contact with the first insulating layer and the microcrystalline semiconductor layer; and

an amorphous semiconductor layer which is provided over the first insulating layer so as to cover the second insulating layer and the microcrystalline semiconductor layer,

wherein the first insulating layer is a silicon nitride layer and the second insulating layer is a silicon oxynitride layer.

2. The thin film transistor according to claim 1, wherein the first insulating layer is thick in a region where the first insulating layer overlaps with the second insulating layer.

3. The thin film transistor according to claim 2, wherein a side surface of the microcrystalline semiconductor layer and a side surface of the second insulating layer are substantially aligned with each other.

4. The thin film transistor according to claim 1, wherein the microcrystalline semiconductor layer comprises an impurity element serving as a donor.

5. The thin film transistor according to claim 1, wherein the amorphous semiconductor layer is an amorphous silicon layer.

6. A display device comprising the thin film transistor according to claim 1.

7. A thin film transistor comprising:

a gate electrode layer;

a first insulating layer which is provided so as to cover the gate electrode layer;

an amorphous semiconductor layer which is provided over the first insulating layer so as to be at least partly in contact with the first insulating layer;

a pair of impurity semiconductor layers forming a source region and a drain region, which are provided with a distance therebetween over the amorphous semiconductor layer;

a microcrystalline semiconductor layer which is provided between the first insulating layer and the amorphous semiconductor layer in part of a channel formation region and which at least partly overlaps with the gate electrode layer and does not overlap with the pair of impurity semiconductor layers; and

a second insulating layer which is provided between and in contact with the first insulating layer and the microcrystalline semiconductor layer,

wherein the first insulating layer is a silicon nitride layer and the second insulating layer is a silicon oxynitride layer.

8. The thin film transistor according to claim 7, wherein the first insulating layer is thick in a region where the first insulating layer overlaps with the second insulating layer.

9. The thin film transistor according to claim 8, wherein a side surface of the microcrystalline semiconductor layer and a side surface of the second insulating layer are substantially aligned with each other.

10. The thin film transistor according to claim 7, wherein the microcrystalline semiconductor layer comprises an impurity element serving as a donor.

11. The thin film transistor according to claim 7, wherein the amorphous semiconductor layer is an amorphous silicon layer.

12. A display device comprising the thin film transistor according to claim 7.

13. A thin film transistor comprising:

a gate electrode layer;

a first insulating layer which is provided so as to cover the gate electrode layer;

a microcrystalline semiconductor layer which is provided over the first insulating layer and which at least partly overlaps with the gate electrode layer;

an amorphous semiconductor layer which is provided so as to cover at least the microcrystalline semiconductor layer;

a pair of impurity semiconductor layers forming a source region and a drain region, which are provided over the amorphous semiconductor layer and which do not overlap with the microcrystalline semiconductor layer; and

a second insulating layer which is provided between and in contact with the first insulating layer and the microcrystalline semiconductor layer,

wherein the first insulating layer is a silicon nitride layer and the second insulating layer is a silicon oxynitride layer.

14. The thin film transistor according to claim 13, wherein the first insulating layer is thick in a region where the first insulating layer overlaps with the second insulating layer.

15. The thin film transistor according to claim 14, wherein a side surface of the microcrystalline semiconductor layer and a side surface of the second insulating layer are substantially aligned with each other.

16. The thin film transistor according to claim 13, wherein the microcrystalline semiconductor layer comprises an impurity element serving as a donor.

17. The thin film transistor according to claim 13, wherein the amorphous semiconductor layer is an amorphous silicon layer.

18. A display device comprising the thin film transistor according to claim 13.

19. A thin film transistor comprising:

a gate electrode layer;

a first insulating layer which is provided so as to cover the gate electrode layer;

a pair of impurity semiconductor layers forming a source region and a drain region, which are provided with a distance therebetween and which at least partly overlap with the gate electrode layer;

a microcrystalline semiconductor layer which is provided over the first insulating layer in part of a channel formation region and which at least partly overlaps with the gate electrode layer and one of the pair of impurity semiconductor layers and does not overlap with the other of the pair of impurity semiconductor layers;

a second insulating layer which is provided between and in contact with the first insulating layer and the microcrystalline semiconductor layer; and

an amorphous semiconductor layer which is provided over the first insulating layer so as to cover the second insulating layer and the microcrystalline semiconductor layer,

wherein the first insulating layer is a silicon nitride layer and the second insulating layer is a silicon oxynitride layer.

20. The thin film transistor according to claim 19, wherein the first insulating layer is thick in a region where the first insulating layer overlaps with the second insulating layer.

21. The thin film transistor according to claim 20, wherein a side surface of the microcrystalline semiconductor layer and a side surface of the second insulating layer are substantially aligned with each other.

22. The thin film transistor according to claim 19, wherein the microcrystalline semiconductor layer comprises an impurity element serving as a donor.

23. The thin film transistor according to claim 19, wherein the amorphous semiconductor layer is an amorphous silicon layer.

24. A display device comprising the thin film transistor according to claim 19.

25. A thin film transistor comprising:

a gate electrode layer;

a first insulating layer which is provided so as to cover the gate electrode layer;

an amorphous semiconductor layer which is provided over the first insulating layer so as to be at least partly in contact with the first insulating layer;

a pair of impurity semiconductor layers forming a source region and a drain region, which are provided with a distance therebetween over the amorphous semiconductor layer;

a microcrystalline semiconductor layer which is provided between the first insulating layer and the amorphous semiconductor layer in part of a channel formation region and which at least partly overlaps with the gate electrode layer and one of the pair of impurity semiconductor layers and does not overlap with the other of the pair of impurity semiconductor layers; and

a second insulating layer which is provided between and in contact with the first insulating layer and the microcrystalline semiconductor layer,

wherein the first insulating layer is a silicon nitride layer and the second insulating layer is a silicon oxynitride layer.

26. The thin film transistor according to claim 25, wherein the first insulating layer is thick in a region where the first insulating layer overlaps with the second insulating layer.

27. The thin film transistor according to claim 26, wherein a side surface of the microcrystalline semiconductor layer and a side surface of the second insulating layer are substantially aligned with each other.

28. The thin film transistor according to claim 25, wherein the microcrystalline semiconductor layer comprises an impurity element serving as a donor.

29. The thin film transistor according to claim 25, wherein the amorphous semiconductor layer is an amorphous silicon layer.

30. A display device comprising the thin film transistor according to claim 25.

31. A thin film transistor comprising:

a gate electrode layer;

a first insulating layer which is provided so as to cover the gate electrode layer;

a microcrystalline semiconductor layer which is provided over the first insulating layer and which at least partly overlaps with the gate electrode layer;

an amorphous semiconductor layer which is provided so as to cover at least the microcrystalline semiconductor layer;

a pair of impurity semiconductor layers forming a source region and a drain region, which are provided over the amorphous semiconductor layer such that one of the pair of impurity semiconductor layers overlaps with the microcrystalline semiconductor layer and the other does not overlap with the microcrystalline semiconductor layer; and

a second insulating layer which is provided between and in contact with the first insulating layer and the microcrystalline semiconductor layer,

wherein the first insulating layer is a silicon nitride layer and the second insulating layer is a silicon oxynitride layer.

32. The thin film transistor according to claim 31, wherein the first insulating layer is thick in a region where the first insulating layer overlaps with the second insulating layer.

33. The thin film transistor according to claim 32, wherein a side surface of the microcrystalline semiconductor layer and a side surface of the second insulating layer are substantially aligned with each other.

34. The thin film transistor according to claim 31, wherein the microcrystalline semiconductor layer comprises an impurity element serving as a donor.

35. The thin film transistor according to claim 31 wherein the amorphous semiconductor layer is an amorphous silicon layer.

36. A display device comprising the thin film transistor according to claim 31.