(110)-oriented p-channel trench MOSFET having high-K gate dielectric

• US 8,039,877 B2
• Filed: 09/09/2008
• Issued: 10/18/2011
• Est. Priority Date: 09/09/2008
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Ngai, Tat, Wang, Qi
• Primary Examiner(s): MANDALA, VICTOR A
• Application Number:
  US12/207,417
• Publication Number:
  US 20100059797A1
• Time in Patent Office: 1,134 Days
• Field of Search: 257/255, 257/330, 257/E29.004, 257/E29.255
• US Class Current: 257/255
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/19043 being a resistor
• CPC Class Codes: H01L 2924/30105 Capacitance
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding

Abstract

A method of forming a field effect transistor having a heavily doped p-type (110) semiconductor layer over a metal substrate starts with providing a heavily doped p-type (110) silicon layer, and forming a lightly doped p-type (110) silicon layer on the P heavily doped-type (110) silicon layer. The method also includes forming a p-channel MOSFET which has a channel region along a (110) crystalline plane in the lightly doped p-type (110) silicon layer to allow a current conduction in a <110> direction. The p-channel MOSFET also includes a gate dielectric layer having a high dielectric constant material lining the (110) crystalline plane. The method further includes forming a top conductor layer overlying the lightly doped p-type (110) silicon layer and a bottom conductor layer underlying the heavily doped p-type (110) silicon layer. A current conduction from the top conductor layer to the bottom conductor layer is characterized by a hole mobility along a <110> crystalline orientation and on a (110) crystalline plane.

Claims

1. A semiconductor device having a heavily doped p-type (110) semiconductor layer overlying a metal substrate, comprising:

a first metal layer;

a first p-type semiconductor layer overlying the first metal layer, the first p-type semiconductor layer being heavily doped and having a surface crystal orientating of (110), the first p-type semiconductor layer being characterized by a first conductivity;

a second p-type semiconductor layer overlying the first p-type semiconductor layer, the second semiconductor layer having a surface crystal orientation of (110) and a second conductivity that is lower than the first conductivity;

a gate dielectric layer including a high dielectric constant material, the gate dielectric layer lining a (110) crystalline plane in the second p-type semiconductor layer; and

a second metal layer overlying the second p-type semiconductor layer,

wherein a current conduction between the first metal layer to the second metal layer is characterized by a hole mobility along a <

110>

crystalline orientation and on (110) crystalline plane.

2. The device of claim 1 wherein the high dielectric constant material has a dielectric constant higher than that of a silicon dioxide.

3. The device of claim 1 wherein the high dielectric constant material has a thickness of about 5 nm to about 50 nm.

4. The device of claim 1 wherein the gate dielectric comprises a high dielectric constant material formed using an atomic layer deposition (ALD).

5. The device of claim 1 wherein the high dielectric constant material includes HfO₂.

6. The device of claim 1 wherein the gate dielectric layer includes a thin interfacial dielectric layer underlying the high dielectric constant material.

7. The device of claim 1 wherein the thin interfacial dielectric layer has a thickness of about 5-10 Å

.

8. The device of claim 1 wherein the gate dielectric layer includes a thin oxide or oxynitride layer underlying the high dielectric constant material.

9. The device of claim 1 wherein the first p-type semiconductor layer has a thickness of not more than about 3 um.

10. The device of claim 1 wherein the first p-type semiconductor layer is characterized by a doping concentration of 1×

10¹⁷ cm<sup>−

3</sup>or higher.

11. The device of claim 1 wherein the first p-type semiconductor layer is characterized by a doping concentration higher than 6×

10¹⁹ cm<sup>−

3</sup>.

12. The device of claim 1 wherein a thickness of the first p-type semiconductor layer is between approximately 0.5 um to approximately 3 um.

13. The device of claim 1 wherein each of the first and second p-type semiconductor layers is an epitaxial layer.

14. The device of claim 1 wherein the bottom metal layer has sufficient thickness for supporting the vertical semiconductor device.

15. The semiconductor device of claim 1 wherein the semiconductor device comprises a trench gate MOSFET, the trench gate MOSFET further comprising:

a trench extending into the second p-type semiconductor region;

a channel region adjacent a trench sidewall along a (110) crystalline plane to allow a current conduction in a <

110>

direction, the gate dielectric layer lining the trench side wall adjacent the channel region;

a gate electrode over the gate dielectric in the trench;

p-type source regions flanking each side of the gate electrode in the trench;

a p-type drift region;

an N-type body region extending over the drift region; and

a p-type drain region including at least a portion of the heavily doped first p-type semiconductor layer.

16. The semiconductor device of claim 1 wherein the semiconductor device comprises a shielded gate trench MOSFET, the shielded gate trench MOSFET further comprising:

a trench extending into the second p-type semiconductor layer;

a shield dielectric lining sidewalls and a bottom surface of the trench;

a shield electrode in a lower portion of the trench, the shield electrode being insulated from the second semiconductor layer by the shield dielectric;

an inter-electrode dielectric overlying the shield electrode;

a channel region adjacent a trench sidewall along a (110) crystalline plane to allow a current conduction in a <

110>

direction, the gate dielectric layer lining the trench side wall adjacent the channel region; and

a gate electrode in an upper portion of the trench over the inter-electrode dielectric, the gate electrode being insulated from the second p-type semiconductor layer by the gate dielectric.

17. The semiconductor device of claim 16 wherein the second p-type semiconductor layer comprises:

a p-type drift region;

an N-type body region extending over the drift region; and

p-type source regions in the body region adjacent to the trench.

18. The semiconductor device of claim 1 wherein the semiconductor device comprises a planar MOSFET device, the planar MOSFET further comprising:

a drain region including at least a portion of the first p-type semiconductor layer;

a drift region including at least a portion of the lightly doped p-type (110) layer;

an N-type well region in an upper portion of the drift region, a surface portion of the N-type well region being configured to provide a current conduction path along a <

110>

direction in an (110) plane;

a heavily doped p-type source region in the N-type well region, a surface portion of the N-type well region between the source region and the drift region being configured as the channel region; and

a gate electrode overlying the gate dielectric which overlies the channel region.

19. A vertical trench gate MOSFET device formed in a (110) substrate, comprising:

a bottom metal layer;

a heavily-doped (110) p-type semiconductor layer overlying the bottom metal layer;

a lightly-doped (110) p-type semiconductor layer overlying heavily-doped (110) p-type semiconductor layer;

an N-type body region in the lightly-doped (110) p-type semiconductor layer; and

a trench extending through the body region and into a bottom portion of the lightly-doped (110) p-type semiconductor layer underlying the body region;

a channel region adjacent a trench sidewall along a (110) crystalline plane to allow a current conduction in a <

110>

direction,

a gate dielectric layer having a high dielectric constant material lining the trench sidewall adjacent the channel region;

a gate electrode over the gate dielectric in the trench;

p-type source regions flanking each side of the gate electrode in the trench;

a p-type drain region including at least a portion of the heavily doped (110) p-type semiconductor layer; and

a top metal layer overlying the lightly-doped (110) p-type semiconductor layer, the top metal layer being coupled to the source regions and the body region; and

wherein the first and the second metal layers provide external contacts for the current conduction in the <

110>

direction.

20. The device of claim 19 wherein the heavily doped (110) p-type semiconductor layer is characterized by a doping concentration of 1×

10¹⁷ cm<sup>−

3</sup>or higher.

21. The device of claim 19 wherein the heavily doped (110) p-type semiconductor layer is characterized by a doping concentration higher than 6×

10¹⁹ cm<sup>−

3</sup>.

22. A vertical shielded gate trench MOSFET device formed in a (110) substrate, comprising:

a bottom metal layer;

a first p-type semiconductor layer overlying the bottom metal layer, the first p-type semiconductor layer being characterized by a surface crystal orientating of (110) and a first conductivity, the first p-type semiconductor layer being heavily doped;

a second p-type semiconductor layer having a surface crystal orientation of (110) and overlying the first p-type semiconductor layer, the second p-type semiconductor layer being characterized by a lower conductivity than the first conductivity;

an N-type body region in the second p-type semiconductor layer;

a trench extending through the body region and into a bottom portion of the second p-type semiconductor layer underlying the body region;

a shield dielectric lining sidewalls and a bottom surface of the trench, the shield dielectric including a first shield oxide layer;

a shield electrode in a lower portion of the trench, the shield electrode being insulated from the semiconductor region by the shield dielectric;

an inter-electrode dielectric overlying the shield electrode;

a channel region adjacent a trench sidewall along a (110) crystalline plane to allow a current conduction in a <

110>

direction,

a gate dielectric layer having a high dielectric constant material lining the trench sidewall adjacent the channel region;

a gate electrode in an upper portion of the trench over the inter-electrode dielectric, the gate electrode being insulated from the semiconductor region by the gate dielectric;

p-type source regions flanking each side of the gate electrode in the trench;

a p-type drain region including at least a portion of the heavily doped (110) p-type semiconductor layer; and

a top metal layer overlying the second p-type semiconductor layer, the top metal layer being coupled to the source regions and the body region,

wherein the first and the second metal layers provide external contacts for the current conduction in the <

110>

direction.

23. The device of claim 22 wherein the first p-type semiconductor layer is characterized by a doping concentration of about 1×

10¹⁷ cm<sup>−

3</sup>or higher.

24. The device of claim 22 wherein the first p-type semiconductor layer is characterized by a doping concentration of about 6×

10¹⁹ cm<sup>−

3</sup>higher.

25. A planar power MOSFET device, the device comprising:

a bottom metal layer;

a heavily-doped (110) p-type drain region overlying the bottom metal layer;

a lightly-doped (110) p-type drift overlying heavily-doped (110) p-type semiconductor layer;

an N-type well region in an upper portion of the drift region, a surface portion of the N-type well region being configured;

a heavily doped p-type source region in the N-type well region, a surface portion of the N-type well region between the source region and the drift region being configured as the channel region to provide a current conduction path along a <

110>

direction in an (110) plane;

a gate dielectric layer having a high dielectric constant material overlying the channel region; and

a gate electrode overlying the gate dielectric which overlies the channel region; and

a top metal layer coupled to the source regions and the body region; and

wherein the top and the bottom metal layers provide external contacts for the current conduction in the <

110>

direction.