Printed circuit board and method thereof and a solder ball land and method thereof

• US 8,039,972 B2
• Filed: 07/13/2009
• Issued: 10/18/2011
• Est. Priority Date: 08/11/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Sin, Wha-su, Kim, Sang-jun, Jung, Ky-hyun, Song, Ho-geon, Kim, Heui-seog, Ko, Jun-young
• Primary Examiner(s): CLARK, SHEILA V
• Application Number:
  US12/458,429
• Publication Number:
  US 20090278249A1
• Time in Patent Office: 827 Days
• Field of Search: 257/786, 257/778, 257/784, 257/780, 257/781
• US Class Current: 257/781
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/16503 comprising an intermetallic compound
• CPC Class Codes: H01L 2224/32057 in side view
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83102 using surface energy, e.g. capillary forces
• CPC Class Codes: H01L 2224/83385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H05K 2201/0391 : Using different types of conductors
• CPC Class Codes: H05K 2201/0989 : Coating free areas, e.g. areas other than pads or lands free of solder resist
• CPC Class Codes: H05K 3/243 : characterised by selective plating, e.g. for finish plating of pads selective plating for making the circuit pattern H05K3/108, H05K3/182
• CPC Class Codes: H05K 3/282 : for inhibiting the corrosion of the circuit, e.g. for preserving the solderability
• CPC Class Codes: H05K 3/3457 : Solder materials or compositions; Methods of application thereof

Abstract

A printed circuit board and method thereof and a solder ball land and method thereof. The example printed circuit board (PCB) may include a first solder ball land having a first surface treatment portion configured for a first type of resistance and a second solder ball land having a second surface treatment portion configured for a second type of resistance. The example solder ball land may include a first surface treatment portion configured for a first type of resistance and a second surface treatment portion configured for a second type of resistance. A first example method may include first treating a first surface of a first solder ball land to increase a first type of resistance and second treating a second surface of a second solder ball land to increase a second type of resistance other than the first type of resistance. A second example method may include first treating a solder ball land to increase a first type of resistance and second treating the solder ball land to increase a second type of resistance other than the first type of resistance.

Claims

1. A printed circuit board (PCB), comprising:

a first metal land having a first surface treatment portion configured for a first type of resistance; and

a second metal land having a second surface treatment portion configured for a second type of resistance, wherein a surface material of the first metal land is different from that of the second metal land, and the first type of resistance is higher heat conductivity which allows for greater heat dissipation and the second type of resistance is higher stress resistance.

2. The PCB of claim 1, further comprising:

a substrate formed of an insulating material;

wherein

connection terminals connected to a semiconductor chip are installed on an upper surface of the substrate, and

the first metal land is disposed on an edge region of the substrate and the second metal land is disposed on a center region of the substrate.

3. The PCB of claim 1, wherein the first surface treatment portion is applied with an organic solderability preservatives (OSP) process.

4. The PCB of claim 1, wherein the second surface treatment portion is applied by sequentially stacking a nickel layer and a gold layer on the second metal land.

5. The PCB of claim 2, wherein the connection terminals includes first connect terminals positioned in the edge region and second connection terminals positioned in the center region.

6. The PCB of claim 1, wherein each of the first and second metal lands include the first and second surface treatment portions with the first and second types of resistance, respectively.

7. The PCB of claim 1, wherein the first metal land does not include the second surface treatment portion and the second metal land does not include the first surface treatment portion.

8. A semiconductor package, comprising:

the PCB of claim 1;

a semiconductor chip mounted on a first surface of the PCB through connection terminals;

first and second solder balls attached to a second surface of the PCB;

a first metal bonding layer formed on a first bonding surface between a first solder ball and a first metal land disposed on an edge region of the second surface of the PCB; and

a second metal bonding layer formed on a second bonding surface between a second solder ball and a second metal land disposed on a center region of the second surface of the PCB.

9. The semiconductor package of claim 8, wherein the first metal land is OSP surface treated before being attached the first solder ball.

10. The semiconductor package of claim 8, wherein the first metal bonding layer includes a copper-tin alloy.

11. The semiconductor package of claim 8, wherein the second metal land is surface treated with nickel and gold layers before being attached to the second solder ball.

12. The semiconductor package of claim 8, wherein the second metal bonding layer includes a nickel-tin alloy.

13. The semiconductor package of claim 8, wherein the semiconductor chip is mounted on the connection terminals through one of a gold wire and a solder bump.

14. The semiconductor package of claim 8, further comprising:

a sealing resin covering the semiconductor chip and the first surface of the PCB.

15. The semiconductor package of claim 8, further comprising:

an underfill at least partially filling a space between the semiconductor chip and the first surface of the PCB.

16. The semiconductor package of claim 10, wherein at least one of the first and second solder balls is a lead-free solder ball.

17. A metal land, comprising:

a first surface treatment portion configured for a first type of resistance and a second surface treatment portion configured for a second type of resistance, wherein the second surface treatment portion is applied by sequentially stacking a nickel layer and a gold layer.

18. The metal land of claim 17, wherein the first type of resistance is higher heat conductivity which allows for greater heat dissipation and the second type of resistance is higher stress resistance.

19. The metal land of claim 17, wherein the first surface treatment portion is applied with an organic solderability preservatives (OSP) process.

20. The metal land of claim 17, wherein the second surface treatment portion protrudes above a surface of the metal land.

21. The metal land of claim 17, wherein the second surface treatment portion is flush with the metal land so as not to protrude from a surface of the metal land.

22. A printed circuit board (PCB), comprising:

a substrate formed of an insulating material;

connection terminals connected to a semiconductor chip installed on an upper surface of the substrate; and

the metal land of claim 17.

23. The PCB of claim 22, wherein the connection terminals include first connection terminals in an edge region of the substrate and second connection terminals positioned in a center region of the substrate.

24. A semiconductor package, comprising:

the PCB of claim 22;

a semiconductor chip mounted on a first surface of the PCB through the connection terminals;

a solder ball attached to a second surface of the PCB; and

first and second metal bonding layers formed on a bonding surface between the solder ball and the metal land.

25. The semiconductor package of claim 24, wherein the first surface treatment portion of the metal land is flush with a surface of the metal land and the second surface treatment portion of the metal land protrudes from the surface of the metal land.

26. The semiconductor package of claim 24, wherein the semiconductor chip is mounted on the PCB through one of a gold wire and a solder bump.

27. The semiconductor package of claim 24, further comprising:

an underfill at least partially filling a space between the first surface of the PCB and the semiconductor chip.

28. The semiconductor package of claim 24, wherein the connection terminals include a compound metal bonding layer with the first metal bonding layer formed on an edge region thereof and the second metal bonding layer formed on a center region thereof.

29. The semiconductor package of claim 24, further comprising:

a sealing resin covering the semiconductor chip and the first surface of the PCB.

30. The semiconductor package of claim 24, wherein the first metal bonding layer includes a copper-tin alloy.

31. The semiconductor package of claim 24, wherein the second metal bonding layer includes a nickel-tin alloy.

32. The semiconductor package of claim 24, wherein the solder ball is a lead-free solder ball.