Flash memory device and layout method of the flash memory device

• US 8,040,726 B2
• Filed: 07/21/2009
• Issued: 10/18/2011
• Est. Priority Date: 11/27/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kwak, Pan-suk
• Primary Examiner(s): Phung; Anh
• Assistant Examiner(s): LE, TOAN K
• Application Number:
  US12/506,357
• Publication Number:
  US 20100128530A1
• Time in Patent Office: 819 Days
• Field of Search: 365/185.05, 365/185.18, 365/185.26, 365/185.29
• US Class Current: 365/185.05
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits

Abstract

Provided is a flash memory device including a plurality of page buffer high voltage transistors. The plurality of high voltage transistors are operatively associated with a page buffer circuit, wherein each high voltage transistor includes; a gate pattern separating a first pattern from a second pattern. The first and second patterns extend in parallel and serve as respective source/drain regions, and the first pattern is floated and the second pattern receives an erase voltage during an erase operation. A first set of high voltage transistors is series connected in a columnar arrangement, such that column adjacent high voltage transistors are laid out with alternating source/drain symmetry in the columnar direction.

Claims

1. A flash memory device comprising:

a plurality of high voltage transistors operatively associated with a page buffer circuit, wherein each high voltage transistor comprises;

a gate pattern separating a first pattern from a second pattern, wherein the first and second patterns extend in parallel and serve as respective source/drain regions, and the first pattern is floated and the second pattern receives an erase voltage during an erase operation, and

wherein a first set of high voltage transistors is series connected in a columnar arrangement, such that column adjacent high voltage transistors are laid out with alternating source/drain symmetry in the columnar direction.

2. The flash memory device of claim 1, wherein source/drain regions of the column adjacent high voltage transistors are separated by a spacing interval of three times a minimum feature size.

3. The flash memory device of claim 2, further comprising:

a second set of high voltage transistors series connected in the columnar arrangement and arranged in a row with the first set of high voltage transistors, such that row adjacent high voltage transistors are separated by a spacing interval of eight time the minimum feature size.

4. The flash memory device of claim 1, further comprising:

a plurality of first voltage lines disposed in parallel and extending in a columnar direction; and

a plurality of second voltage lines disposed in parallel and extending in the columnar direction;

wherein first patterns of the high voltage transistors in the first set of high voltage transistors are respectively connected to one of the plurality of first voltage lines and second patterns of the high voltage transistors in the first set of high voltage transistors are respectively connected to one of the plurality of second voltage lines.

5. The flash memory device of claim 4, wherein the plurality of first voltage lines and the plurality of second voltage lines vertically overlap as disposed at different material layers within the flash memory device.

6. The flash memory device of claim 5, wherein one end of the series connected first set of high voltage transistors is connected to a corresponding page buffer circuit through a low voltage transistor.

7. A layout method for a flash memory device, the method comprising:

defining a plurality of high voltage transistors operatively associated with a page buffer circuit, wherein each high voltage transistor comprises;

a gate pattern separating a first pattern from a second pattern, wherein the first and second patterns extend in parallel and serve as respective source/drain regions;

defining a series connected first set of high voltage transistors in a columnar arrangement, such that column adjacent high voltage transistors are laid out with alternating source/drain symmetry in the columnar direction; and

defining voltage line connections to the first set of high voltage transistors, such that during an erase operation each respective first pattern is floated and each respective second pattern receives an erase voltage.

8. The layout method of claim 7, wherein source/drain regions for the column adjacent high voltage transistors are defined as being separated by a spacing interval of three times a minimum feature size.

9. The layout method of claim 8, further comprising:

defining a second set of high voltage transistors series connected in the columnar arrangement and arranged in a row with the first set of high voltage transistors, such that row adjacent high voltage transistors are defined as being separated by a spacing interval of eight time the minimum feature size.

10. The layout method of claim 7, further comprising:

defining a plurality of first voltage lines disposed in parallel and extending in a columnar direction; and

defining a plurality of second voltage lines disposed in parallel and extending in the columnar direction;

wherein first patterns of the high voltage transistors in the first set of high voltage transistors are respectively connected to one of the plurality of first voltage lines and second patterns of the high voltage transistors in the first set of high voltage transistors are respectively connected to one of the plurality of second voltage lines.

11. The layout method of claim 10, wherein the plurality of first voltage lines and the plurality of second voltage lines are defined to vertically overlap within the flash memory device.

12. The layout method of claim 11, wherein the first set of high voltage transistors is defined to connect to a corresponding page buffer circuit through a low voltage transistor.