NAND memory device column charging

• US 8,040,732 B2
• Filed: 08/06/2010
• Issued: 10/18/2011
• Est. Priority Date: 03/01/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F.
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US12/852,075
• Publication Number:
  US 20100296346A1
• Time in Patent Office: 438 Days
• Field of Search: 365/185.18, 365/185.24
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

Embodiments of NAND Flash memory devices and methods recognize that effective column coupling capacitance can be reduced by maintaining a sourced voltage on adjacent columns of an array. Maintaining the columns in a charged state prior to array operations (read, write, and program) reduces current surges and improves data read timing. Devices and methods charge the array columns at pre-charge and following array access operations.

Claims

1. A method of operating a memory array, wherein the memory array comprises a plurality of bit lines, and wherein each of the bit lines can be selectively coupled to a respective series of memory cells, the method comprising:

charging adjacent ones of the bit lines as part of powering up the memory array prior to an operation of the array; and

performing the operation of the array while maintaining charge on unselected ones of the bit lines.

2. The method of claim 1, wherein charging adjacent ones of the bit lines as part of powering up the memory array prior to an operation of the array comprises charging the adjacent ones of the bit lines upon power-up of a device including the array.

3. The method of claim 1, wherein charging adjacent ones of the bit lines as part of powering up the memory array prior to an operation of the array comprises charging the adjacent ones of the bit lines at power-up of a device including the array.

4. The method of claim 1, wherein charging adjacent ones of the bit lines as part of powering up the memory array prior to an operation of the array comprises charging the adjacent ones of the bit lines during power-up of a device including the array.

5. The method of claim 1, wherein charging adjacent ones of the bit lines as part of powering up the memory array prior to an operation of the array comprises charging the adjacent ones of the bit lines following power-up of a device including the array.

6. The method of claim 1, wherein charging adjacent ones of the bit lines comprises charging adjacent ones of the bit lines to a positive voltage.

7. The method of claim 1, wherein the operation comprises a read operation.

8. The method of claim 1, wherein the operation comprises a verify operation.

9. The method of claim 1, wherein the operation comprises a write operation.

10. The method of claim 1, wherein the operation comprises a program operation.

11. The method of claim 1, wherein the operation comprises an erase operation.

12. The method of claim 1, wherein performing the operation comprises performing a sensing operation on selected ones of the bit lines, wherein the unselected ones of the bit lines remain charged.

13. A method of operating a memory array, wherein the memory array comprises a plurality of bit lines, and wherein each of the bit lines can be selectively coupled to a respective series of memory cells, the method comprising:

charging adjacent ones of the bit lines prior to an operation of the array;

performing a sensing operation on selected ones of the bit lines; and

maintaining unselected ones of the bit lines in a charged state while sensing the selected ones of the bit lines, until a subsequent operation of the array.

14. The method of claim 13, further comprising charging the selected bit lines after performing the sensing operation.

15. The method of claim 13, wherein the operation comprises a read operation.

16. The method of claim 13, wherein the operation comprises a verify operation.

17. The method of claim 13, wherein each of the unselected ones of the bit lines is adjacent to a respective one of the selected bit lines.

18. The method of claim 13, wherein the selected ones of the bit lines correspond to a first active page of data and the unselected ones of the bit lines correspond to a second inactive page of data.

19. The method of claim 13, further comprising re-charging discharged ones of the bit lines after performing the operation.

20. The method of claim 13, wherein charging adjacent ones of the bit lines prior to an operation of the array comprises charging adjacent ones of the bit lines prior to a first operation of the array.

21. The method of claim 13, wherein charging adjacent ones of the bit lines comprises charging adjacent ones of the bit lines to a supply voltage.

22. A method of operating a memory array, wherein the memory array comprises a plurality of bit lines, and wherein each of the bit lines can be selectively coupled to a respective series of memory cells, the method comprising:

maintaining adjacent ones of the bit lines in a charged state prior to an operation of the array;

performing the operation of the array using selected ones of the bit lines while maintaining the charged state of unselected ones of the bit lines; and

re-charging the selected ones of the bit lines to the charged state after performing the operation and prior to a subsequent operation of the array.

23. A method of operating a memory array, wherein the memory array comprises a plurality of bit lines, and wherein each of the bit lines can be selectively coupled to a respective series of memory cells, the method comprising:

maintaining a sourced voltage on adjacent ones of the bit lines prior to an operation of the array;

performing the operation of the array using selected ones of the bit lines while maintaining the sourced voltage on unselected ones of the bit lines; and

re-applying the sourced voltage to the selected ones of the bit lines after performing the operation and prior to a subsequent operation of the array.