NAND memory device column charging
First Claim
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1. A method of operating a memory array, wherein the memory array comprises a plurality of bit lines, and wherein each of the bit lines can be selectively coupled to a respective series of memory cells, the method comprising:
- charging adjacent ones of the bit lines as part of powering up the memory array prior to an operation of the array; and
performing the operation of the array while maintaining charge on unselected ones of the bit lines.
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Abstract
Embodiments of NAND Flash memory devices and methods recognize that effective column coupling capacitance can be reduced by maintaining a sourced voltage on adjacent columns of an array. Maintaining the columns in a charged state prior to array operations (read, write, and program) reduces current surges and improves data read timing. Devices and methods charge the array columns at pre-charge and following array access operations.
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Citations
23 Claims
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1. A method of operating a memory array, wherein the memory array comprises a plurality of bit lines, and wherein each of the bit lines can be selectively coupled to a respective series of memory cells, the method comprising:
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charging adjacent ones of the bit lines as part of powering up the memory array prior to an operation of the array; and performing the operation of the array while maintaining charge on unselected ones of the bit lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of operating a memory array, wherein the memory array comprises a plurality of bit lines, and wherein each of the bit lines can be selectively coupled to a respective series of memory cells, the method comprising:
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charging adjacent ones of the bit lines prior to an operation of the array; performing a sensing operation on selected ones of the bit lines; and maintaining unselected ones of the bit lines in a charged state while sensing the selected ones of the bit lines, until a subsequent operation of the array. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21)
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22. A method of operating a memory array, wherein the memory array comprises a plurality of bit lines, and wherein each of the bit lines can be selectively coupled to a respective series of memory cells, the method comprising:
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maintaining adjacent ones of the bit lines in a charged state prior to an operation of the array; performing the operation of the array using selected ones of the bit lines while maintaining the charged state of unselected ones of the bit lines; and re-charging the selected ones of the bit lines to the charged state after performing the operation and prior to a subsequent operation of the array.
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23. A method of operating a memory array, wherein the memory array comprises a plurality of bit lines, and wherein each of the bit lines can be selectively coupled to a respective series of memory cells, the method comprising:
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maintaining a sourced voltage on adjacent ones of the bit lines prior to an operation of the array; performing the operation of the array using selected ones of the bit lines while maintaining the sourced voltage on unselected ones of the bit lines; and re-applying the sourced voltage to the selected ones of the bit lines after performing the operation and prior to a subsequent operation of the array.
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Specification