Specialized processing block for programmable logic device

• US 8,041,759 B1
• Filed: 06/05/2006
• Issued: 10/18/2011
• Est. Priority Date: 02/09/2006
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Azgomi, Orang, Pelt, Robert L., Lee, Kwan Yee Martin, Langhammer, Martin, Streicher, Keone
• Primary Examiner(s): Bullock, Jr.; Lewis
• Assistant Examiner(s): SANDIFER, MATTHEW D
• Application Number:
  US11/447,370
• Time in Patent Office: 1,961 Days
• Field of Search: 708290-409, 326 37- 39
• US Class Current: 708/523
• CPC Class Codes: H03K 19/177 arranged in matrix form

Abstract

A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured for various digital signal processing operations, including finite impulse response (FIR) filters and infinite impulse response (IIR) filters. By using the programmable connections, and in some cases the programmable resources of the programmable logic device, and by running portions of the specialized processing block at higher clock speeds than the remainder of the programmable logic device, more complex FIR and IIR filters can be implemented.

Claims

1. A specialized processing block for a programmable logic device, said specialized processing block being adaptable to form a finite impulse response (FIR) filter, said specialized processing block comprising:

a plurality of fundamental processing units, each of said fundamental processing units including;

a plurality of partial product generators, each respective one of said partial product generators providing a respective plurality of vectors representing a respective partial product;

compressor circuitry that compresses each respective plurality of vectors into a smaller number of vectors representing said respective partial product; and

circuitry for adding, in one operation, partial products represented by said smaller number of vectors produced by all of said plurality of partial product generators, each said respective partial product being unroutable to any output of said specialized processing block, thereby being unavailable for output, except after being added, by said circuitry for adding, to other of said respective partial products;

a first plurality of input registers for inputting coefficients of said FIR filter as inputs to said plurality of partial product generators;

a second plurality of input registers for inputting data to said FIR filter, said registers being chained for inputting data seriatim to each said plurality of partial product generators; and

an output stage, said output stage including;

a plurality of adders, said plurality of adders being adaptable to provide as an output a sum of (1) a multiplication operation involving two of said fundamental processing units and (2) a corresponding output cascaded from another said plurality of adders in a first other output stage in a first other one of said specialized processing blocks, and

an output cascade register for registering said output for cascading to a second other output stage in a second other one of said specialized processing blocks;

wherein;

said second plurality of input registers comprises a delay register to compensate for said output cascade register when said second plurality of input registers are chained to a corresponding second plurality of input registers in said second other one of said specialized processing blocks.

2. The specialized processing block of claim 1 further comprising:

loopback circuitry for feeding back output of one of said adders to at least one of said partial product generators.

3. The specialized processing block of claim 2 wherein said loopback circuitry further comprises first and second delay elements;

wherein;

said output of said one of said adders is delayed once for feeding back to a respective first partial product generator in each of said fundamental processing units;

said output of said one of said adders is delayed twice for feeding back to a respective second partial product generator in each of said fundamental processing units; and

said specialized processing block is adaptable as a cascade form infinite impulse response filter.

4. A programmable logic device adaptable to form a finite impulse response (FIR) filter, said programmable logic device comprising:

at least one specialized processing block, each said specialized processing block comprising;

a plurality of fundamental processing units, each of said fundamental processing units including;

a plurality of partial product generators, each respective one of said partial product generators providing a respective plurality of vectors representing a respective partial product;

compressor circuitry that compresses each respective plurality of vectors into a smaller number of vectors representing said respective partial product; and

circuitry for adding, in one operation, partial products represented by said smaller number of vectors produced by all of said plurality of partial product generators, each said respective partial product being unroutable to any output of said specialized processing block, thereby being unavailable for output, except after being added, by said circuitry for adding, to other of said respective partial products; and

an output stage, said output stage including a plurality of adders, said plurality of adders being adaptable to provide as an output a sum of (1) a multiplication operation involving two of said fundamental processing units and (2) a corresponding output cascaded from another said plurality of adders in a first other output stage in a first other one of said specialized processing blocks;

each said specialized processing block further comprising;

an output cascade register for registering said output for cascading to a second other output stage in a second other one of said specialized processing blocks;

said programmable logic device further comprising;

a first plurality of input registers for inputting data to said FIR filter, said registers being chained for inputting data seriatim to each said plurality of partial product generators; and

a delay register chained with said first plurality of input registers to compensate for said output cascade register when said first plurality of input registers are chained to a corresponding first plurality of input registers in said second other one of said specialized processing blocks.

5. The programmable logic device of claim 4 wherein:

each of said fundamental processing units comprises two partial product generators;

said plurality of fundamental processing units comprises at least two said fundamental processing units arranged in groupings of two said fundamental processing units; and

said plurality of adders in said output stage comprises two adders for each said grouping, said two adders being configurable to perform one of (a) said sum of (1) said multiplication operation involving two of said fundamental processing units and (2) said corresponding output cascaded from said other of said plurality of adders in said first other output stage in said first other one of said specialized processing blocks, and (b) two additions each providing a respective sum of (1) an output of a respective one of said fundamental processing units and (2) a corresponding output cascaded from another said plurality of adders in another output stage in another one of said specialized processing blocks, said output stage having two cascade outputs;

wherein;

said programmable logic device is adaptable to implement any one of a Fast Fourier Transform butterfly filter and a complex FIR filter.

6. The programmable logic device of claim 4 wherein said first plurality of input registers and said delay register are incorporated in said specialized processing block.

7. The programmable logic device of claim 4 further comprising a second plurality of input registers for inputting coefficients of said FIR filter as inputs to said plurality of partial product generators.

8. The programmable logic device of claim 4 wherein said first plurality of input registers has a one-to-one correspondence with said plurality of partial product generators, said FIR filter being a regular single-channel FIR filter.

9. The programmable logic device of claim 4 wherein:

said first plurality of input registers has a two-to-one correspondence with said plurality of partial product generators; and

respective pairs of said input registers are paired as inputs to said partial product generators;

said programmable logic device further comprising;

logic outside said specialized processing block programmable as soft adders, said soft adders combining said respective pairs of input registers into respective single inputs to said partial product generators;

wherein;

said FIR filter is a regular single-channel symmetrical FIR filter.

10. The programmable logic device of claim 9 wherein:

said plurality of partial product generators in said specialized processing block comprises n partial product generators;

said FIR filter comprises m said specialized processing blocks and p=mn of said partial product generators;

said first plurality of input registers comprises a chain of q=2p of said input registers in said logic outside said specialized processing block;

a first half of said chain comprising p said input registers has one said delay register after every n said input registers

a second half of said chain comprising p said input registers lacks any said delay registers;

said logic outside said processing block includes p said soft adders; and

each rth one of said p soft adders adds an rth one of said q input registers to a (q−

r+1)th of said q input registers.

11. The programmable logic device of claim 4 wherein:

said programmable logic device has a device clock speed;

said partial product generators and said circuitry for adding operate at a second clock speed faster than said device clock speed;

said output stage operates at said device clock speed; and

during one cycle of said second clock speed, said partial product generators and said circuitry for adding process one set of data to produce results that are accumulated such that during one cycle of said device clock speed said partial product generators and said circuitry for adding process a plurality of sets of data;

wherein;

said programmable logic device implements a single-channel semi-parallel FIR filter.

12. The programmable logic device of claim 11 wherein said plurality of sets of data comprises two sets of data.

13. The programmable logic device of claim 11 wherein:

said specialized processing block comprises an accumulator upstream of said output stage; and

said accumulator upstream of said output stage operates at said second clock speed.

14. The programmable logic device of claim 11 wherein:

said specialized processing block comprises an accumulator downstream of said output stage; and

said accumulator downstream of said output stage operates at said device clock speed.

15. The programmable logic device of claim 4 wherein:

said programmable logic device has a device clock speed;

said partial product generators, said circuitry for adding and said output stage operate at a second clock speed faster than said device clock speed;

said programmable logic device further comprises a multiplexer upstream of said first plurality of input registers and a demultiplexer downstream of said output stage; and

during one cycle of said device clock speed said partial product generators, said circuitry for adding and said output stage process a plurality of sets of data;

wherein;

said programmable logic device implements a multi-channel parallel FIR filter.

16. The programmable logic device of claim 15 wherein said plurality of sets of data comprises two sets of data.

17. The programmable logic device of claim 4 wherein:

said programmable logic device has a device clock speed;

said partial product generators and said circuitry for adding operate at a second clock speed at least four times said device clock speed;

said output stage operates at a third clock speed at least twice said device clock speed; and

during one cycle of said second clock speed, said partial product generators and said circuitry for adding process one set of data to produce results that are accumulated such that during one cycle of said third clock speed said partial product generators and said circuitry for adding process a plurality of sets of data;

said programmable logic device further comprising;

a multiplexer upstream of said first plurality of input registers and a demultiplexer downstream of said output stage;

wherein;

during one cycle of said device clock speed said partial product generators, said circuitry for adding and said output stage process a plurality of said plurality of sets of data;

wherein;

said programmable logic device implements a multi-channel semi-parallel FIR filter.

18. A programmable logic device adaptable to form an interpolation filter, said programmable logic device comprising:

at least one specialized processing block, each said specialized processing block comprising;

a plurality of fundamental processing units, each of said fundamental processing units including;

a plurality of partial product generators, each respective one of said partial product generators providing a respective plurality of vectors representing a respective partial product;

compressor circuitry that compresses each respective plurality of vectors into a smaller number of vectors representing said respective partial product; and

circuitry for adding, in one operation, partial products represented by said smaller number of vectors produced by all of said plurality of partial product generators, each said respective partial product being unroutable to any output of said specialized processing block, thereby being unavailable for output, except after being added, by said circuitry for adding, to other of said respective partial products; and

an output stage, said output stage including a plurality of adders, said plurality of adders being adaptable to provide as an output a sum of (1) a multiplication operation involving at least two of said fundamental processing units and (2) a corresponding output cascaded from another said plurality of adders in a first other output stage in a first other one of said specialized processing blocks;

each said specialized processing block further comprising;

an output cascade register for registering said output for cascading to a second other output stage in a second other one of said specialized processing blocks;

said programmable logic device further comprising;

a first plurality of input registers for inputting data to said interpolation filter, said registers being chained for inputting data seriatim to each said plurality of partial product generators;

a delay register chained with said first plurality of input registers to compensate for said output cascade register when said first plurality of input registers are chained to a corresponding first plurality of input registers in said second other one of said specialized processing blocks; and

a plurality of respective second inputs to said plurality of partial product generators;

wherein;

said programmable logic device has a device clock speed;

said partial product generators, said circuitry for adding and said output stage operate at a second clock speed faster than said device clock speed; and

during one cycle of said device clock speed, said partial product generators and said circuitry for adding process one set of data against multiple sets of coefficients on said second inputs to produce multiple sets of results that are output during said one cycle of said device clock speed.

19. A programmable logic device adaptable to form a decimation filter, said programmable logic device comprising:

at least one specialized processing block, each said specialized processing block comprising;

a plurality of fundamental processing units, each of said fundamental processing units including;

a plurality of partial product generators, each respective one of said partial product generators providing a respective plurality of vectors representing a respective partial product;

compressor circuitry that compresses each respective plurality of vectors into a smaller number of vectors representing said respective partial product; and

circuitry for adding, in one operation, partial products represented by said smaller number of vectors produced by all of said plurality of partial product generators, each said respective partial product being unroutable to any output of said specialized processing block, thereby being unavailable for output, except after being added, by said circuitry for adding, to other of said respective partial products; and

an output stage, said output stage including a plurality of adders, said plurality of adders being adaptable to provide as an output a sum of (1) a multiplication operation involving at least two of said fundamental processing units and (2) a corresponding output cascaded from another said plurality of adders in a first other output stage in a first other one of said specialized processing blocks;

each said specialized processing block further comprising;

an output cascade register for registering said output for cascading to a second other output stage in a second other one of said specialized processing blocks;

said programmable logic device further comprising;

a first plurality of input registers for inputting data to said decimation filter, said registers being chained for inputting data seriatim to each said plurality of partial product generators; and

a delay register chained with said first plurality of input registers to compensate for said output cascade register when said first plurality of input registers are chained to a corresponding first plurality of input registers in said second other one of said specialized processing blocks;

wherein;

said programmable logic device has a device clock speed;

said partial product generators and said circuitry for adding operate at a second clock speed at least four times said device clock speed;

said output stage operates at a third clock speed at least twice said device clock speed; and

during one cycle of said second clock speed, said partial product generators and said circuitry for adding process one set of data to produce results that are accumulated such that during one cycle of said third clock speed said partial product generators and said circuitry for adding process a plurality of sets of data;

said programmable logic device further comprising;

a multiplexer upstream of said first plurality of input registers and a demultiplexer downstream of said output stage;

wherein;

during one cycle of said device clock speed said partial product generators, said circuitry for adding and said output stage process a plurality of said plurality of sets of data, all of said sets of data being accumulated across cycles of said third clock speed.

20. A programmable logic device adaptable to form a finite impulse response (FIR) lattice filter, said programmable logic device comprising:

a plurality of specialized processing blocks, each said specialized processing block comprising;

a plurality of fundamental processing units, each of said fundamental processing units including;

a plurality of partial product generators, each respective one of said partial product generators providing a respective plurality of vectors representing a respective partial product;

compressor circuitry that compresses each respective plurality of vectors into a smaller number of vectors representing said respective partial product; and

circuitry for adding, in one operation, partial products represented by said smaller number of vectors produced by all of said plurality of partial product generators, each said respective partial product being unroutable to any output of said specialized processing block, thereby being unavailable for output, except after being added, by said circuitry for adding, to other of said respective partial products;

wherein;

each of said specialized processing blocks comprises at least one register and computes one stage of said FIR lattice filter, where;

each stage is represented by terms f_k(n) and g_k(n),

k represents a stage,

n represents a sample, and

each of f_k(n) and g_k(n) is expressed in terms of f_k-1(n) and g_k-1(n−

1);

for any kth stage, f_k(n) is computed by one said fundamental processing unit forming a sum of (a) a product of (1) f_k-1(n) and (2) 1, and (b) a product of (1) g_k-1(n−

1) and (2) a coefficient Γ

_k; and

for any kth stage, g_k(n) is computed by one said fundamental processing unit forming a sum of (a) a product of (1) f_k-1(n) and (2) a coefficient Γ

_k, and (b) a product of (1) g_k-1(n−

1) and (2) 1, and g_k(n) is delayed by registration in one said at least one register to provide g_k(n−

1);

wherein;

f_k(n) and g_k(n−

1) from the kth stage are available as f_k-1(n) and g_k-1(n−

1) for a (k+1)th stage.

21. A programmable logic device adaptable to form an infinite impulse response (IIR) lattice filter, said programmable logic device comprising:

a plurality of specialized processing blocks, each said specialized processing block comprising;

a plurality of fundamental processing units, each of said fundamental processing units including;

a plurality of partial product generators, each respective one of said partial product generators providing a respective plurality of vectors representing a respective partial product;

compressor circuitry that compresses each respective plurality of vectors into a smaller number of vectors representing said respective partial product; and

circuitry for adding, in one operation, partial products represented by said smaller number of vectors produced by all of said plurality of partial product generators, each said respective partial product being unroutable to any output of said specialized processing block, thereby being unavailable for output, except after being added, by said circuitry for adding, to other of said respective partial products; and

loopback circuitry for feeding back an output of said specialized processing block to an input of said specialized processing block;

wherein;

each of said specialized processing blocks computes one stage of said IIR lattice filter, where;

each stage is represented by terms f_k(n) and g_k(n),

k represents a stage,

n represents a sample, and

each of f_k(n) and g_k(n) is expressed in terms of f_k-1(n) and g_k-1(n−

1);

for any (k−

1)th stage, f_k-1(n) is computed by a first said fundamental processing unit forming a sum of (a) a product of (1) f_k(n), which is derived from a kth stage, and (2) 1, and (b) a product of (1) g_k-1(n−

1) and (2) a coefficient −

Γ

_k; and

for any kth stage, g_k(n) is computed by a second said fundamental processing unit forming a sum of (a) a product of (1) f_k-1(n), which is looped back from said first fundamental processing unit via said loopback circuitry, and (2) a coefficient Γ

_k, and (b) a product of (1) g_k-1(n−

1) and (2) 1, and g_k(n) is delayed by registration to provide g_k(n−

1);

wherein;

f_k(n) and g_k(n−

1) from the kth stage are available as f_k-1(n) and g_k-1(n−

1) for a (k+1)th stage.

22. The programmable logic device of claim 21 wherein outputs of said k stages are concatenated in a tapped delay line to form a pole-zero lattice filter.

23. A specialized processing block for a programmable logic device, said specialized processing block comprising:

a plurality of fundamental processing units, each of said fundamental processing units including;

a plurality of partial product generators, each respective one of said partial product generators providing a respective plurality of vectors representing a respective partial product;

compressor circuitry that compresses each respective plurality of vectors into a smaller number of vectors representing said respective partial product; and

circuitry for adding, in one operation, partial products represented by said smaller number of vectors produced by all of said plurality of partial product generators, each said respective partial product being unroutable to any output of said specialized processing block, thereby being unavailable for output, except after being added, by said circuitry for adding, to other of said respective partial products; and

an output stage, said output stage including;

for each pair of fundamental processing units of said specialized processing block, a corresponding pair of adders, said pair of adders being adaptable to provide as an output one of (a) an output of a multiplication operation involving both of said fundamental processing units, and (b) two separate sums, one for each respective one of said fundamental processing units, each respective sum being a sum of (1) a multiplication operation involving said fundamental processing unit and (2) a corresponding output cascaded from another said respective adder in another output stage in another one of said specialized processing blocks.

24. The programmable logic device of claim 23 wherein a plurality of said specialized processing blocks are adaptable to be configured as an FFT butterfly filter.

25. The programmable logic device of claim 23 wherein a plurality of said specialized processing blocks are adaptable to be configured as a complex FIR filter, wherein each respective adder in said pair of adders is part of a respective chain, one said respective chain being a real part of output of said filter and one said respective chain being an imaginary part of output of said filter.

26. A specialized processing block for a programmable logic device, said specialized processing block comprising:

a plurality of fundamental processing units, each of said fundamental processing units including;

a plurality of partial product generators, each respective one of said partial product generators providing a respective plurality of vectors representing a respective partial product;

compressor circuitry that compresses each respective plurality of vectors into a smaller number of vectors representing said respective partial product; and

circuitry for adding, in one operation, partial products represented by said smaller number of vectors produced by all of said plurality of partial product generators, each said respective partial product being unroutable to any output of said specialized processing block, thereby being unavailable for output, except after being added, by said circuitry for adding, to other of said respective partial products; and

an output stage, said output stage including;

for each pair of fundamental processing units of said specialized processing block, a corresponding pair of adders, said pair of adders being adaptable to provide as an output one of (a) an output of a multiplication operation involving both of said fundamental processing units, and (b) a cascade of said output of said multiplication operation with a corresponding output of a multiplication operation from a corresponding output stage associated with two other said fundamental processing units.

27. The programmable logic device of claim 26 wherein a plurality of said specialized processing blocks are adaptable to be configured as a Cascade Form IIR filter.