Autodetection of a PCI express device operating at a wireless RF mitigation frequency

• US 8,041,844 B2
• Filed: 12/29/2004
• Issued: 10/18/2011
• Est. Priority Date: 12/29/2004
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Martwick, Andrew W., Hunsaker, Mikal C., Vadivelu, Karthi
• Primary Examiner(s): Hafiz; Tariq
• Assistant Examiner(s): YU, HENRY W
• Application Number:
  US11/026,968
• Publication Number:
  US 20060143338A1
• Time in Patent Office: 2,484 Days
• Field of Search: None
• US Class Current: 710/8
• CPC Class Codes: G06F 13/4295 using an embedded synchronisation
• CPC Class Codes: G06F 2213/0026 PCI express
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation

Abstract

A computer system that detects for a PCI Express compliant endpoint device is described. Specifically, the computer system clocks transmit and receive circuits at a first frequency and initiates a training sequence. If the endpoint device successfully trains at the first frequency, the endpoint device is PCI Express compliant. Otherwise, the computer system initiates another training sequence at a second frequency.

Claims

1. A computer system, comprising:

a microprocessor;

a controller coupled to the microprocessor;

the controller being adapted to be wirelessly coupled to a wireless device that is adapted to transmit data at a wireless frequency;

the controller having a root port including a transmitter to transmit to the wireless device and a receiver to receive from the wireless device, the receiver adapted to attempt to train the wireless device at a default frequency and in response to the receiver failing to train the wireless device at the default frequency after N attempts where N is an integer greater than or equal to 1, the root port is adapted to steer the receiver to attempt to train the wireless device at the wireless frequency, wherein the transmitter is adapted to transmit information at the default frequency during the receiver attempting to train the wireless device at the wireless frequency, and wherein the root port is adapted to steer the transmitter to transmit information at the wireless frequency in response to the receiver successfully training the wireless device at the wireless frequency.

2. The computer system of claim 1, wherein the controller further comprises:

a phased locked loop to generate a first clock signal at the default frequency;

a clock divider to divide the first clock signal by an integer to generate a second clock signal at the wireless frequency;

wireless extension logic to provide a first signal in response to failing to train the device at the default frequency a first number of times; and

multiplexer logic to select between the first clock signal at the default frequency and the second clock signal at the wireless clock frequency independently for the receiver and the transmitter, wherein the first clock signal is selected by default and the second clock signal is selected in response to the first signal being provided by the wireless extension state machine.

3. The computer system of claim 1, wherein the wireless frequency is ⅓

of the default frequency.

4. The computer system of claim 1, wherein in response to the device being successfully trained by the receiver at the wireless frequency, the transmitter is steered to operate at the wireless frequency.

5. A method, comprising:

transmitting data from a transmitter in a port at a first frequency to an external device;

clocking a receiver in the port at the first frequency;

sampling an incoming signal received by the receiver from the external device at the first frequency;

determining if the first frequency is the correct frequency for sampling the incoming signal;

clocking the receiver at a second frequency to sample the incoming signal received by the receiver at the second frequency in response to determining the first frequency is not the correct frequency for sampling the incoming signal; and

determining if the second frequency is the correct frequency for sampling the incoming signal;

transmitting an output signal with the transmitter at the first frequency during determining if the second frequency is the correct frequency for sampling the incoming signal; and

transmitting the output signal with the transmitter at the second frequency in response to determining the second frequency is the correct frequency for sampling the incoming signal.

6. The method of claim 5, wherein determining if the first frequency is the correct frequency for sampling the incoming signal comprises determining if the sampling at the first frequency is locking onto specific bits and identifying symbol boundaries in the incoming signal.

7. The method of claim 6, wherein identifying symbol boundaries within the incoming signal comprises identifying a unique symbol within the incoming signal.

8. The method of claim 5, wherein determining if the first frequency is the correct frequency for sampling the incoming signal further comprises determining a predetermined number of times if the sampling at the first frequency is locking onto specific bits and identifying symbol boundaries in the incoming signal, wherein the predetermined number of times is greater than one.

9. The method of claim 8, further comprising:

clocking the transmitter at the second frequency in response to determining the second frequency is the correct frequency for sampling the incoming signal.

10. The method of claim 9, further comprising:

executing a training sequence at the second frequency after clocking the transmitter at the second frequency.

11. The method of claim 5, wherein the first frequency is an integer multiple of the second frequency.

12. An apparatus comprising:

a device including,

receiver logic, while operating at a first frequency, to attempt a predetermined number of times to determine boundaries of data to be received from an endpoint device, the predetermined number of times being greater than one, wherein the receiver logic is to attempt to determine boundaries of data to be received from the endpoint device at a second frequency in response to not determining boundaries of data to be received from the endpoint device the predetermined number of times while operating at the first frequency; and

transmitter logic to transmit data to the endpoint device at the first frequency during the receiver logic to attempt to determine boundaries of data to be received from the endpoint device at the second frequency, wherein the transmitter logic is to transmit data to the endpoint device at the second frequency in response to the receiver logic determining boundaries of data received from the endpoint device, while the receiver logic is operating at the second frequency.

13. The apparatus of claim 12, wherein receiver logic, while operating at a first frequency, to attempt a predetermined number of times to determine boundaries of data received from an endpoint device comprises the receiver logic attempting to properly lock onto specific bits within data received from the endpoint device to identify boundaries of a training symbol.

14. The apparatus of claim 13, further comprising link training logic to determine if the receiver logic properly locks onto specific bits within data received from the endpoint device to identify boundaries of a training symbol.

15. The apparatus of claim 12, further comprises clocking logic to provide a first clock at the first frequency and a second clock at the second frequency;

and selection logic to provide the second clock to the receiver logic in response to the receiver logic not determine boundaries of data received from the endpoint device the predetermined number of times while operating at the first frequency and to provide the second clock to the transmitter logic in response to the receiver logic determine boundaries of data received from the endpoint device, while the receiver logic is operating at the second frequency.

16. An apparatus comprising:

receiver logic in a port to attempt to identify pattern boundaries of an incoming signal to be received from an external device at a first frequency a predetermined number of times; and

clocking logic coupled to the receiver logic and to transmitter logic, the clocking logic to maintain the first frequency to the transmitter logic and to provide a second frequency to the receiver logic in response to the receiver logic not identifying pattern boundaries at the first frequency the predetermined number of times, wherein the clocking logic is further to provide the second frequency to the transmitter logic in response to the receiver logic identifying pattern boundaries at the second frequency within the predetermined number of times;

the transmitter logic to transmit data to the external device at the first frequency during the clocking logic providing the second frequency to the receiver logic in response to the clocking logic maintaining the first frequency to the transmitter logic and to transmit data to the external device at the second frequency in response to the clocking logic provide the section frequency to the transmitter logic.

17. The apparatus of claim 16, wherein the receiver logic is to attempt to identify pattern boundaries at the second frequency a second number of times in response to the clocking logic providing the second frequency to the receiver logic, and wherein the clocking logic is to provide the second frequency to the transmitter logic in response to the receiver logic successfully identifying pattern boundaries at the second frequency.

18. The apparatus of claim 17, the transmitter and receiver logic is associated with physical layer logic of layered stack protocol logic, the layered stack protocol logic including the physical layer logic, link layer logic, and transaction layer logic.