Flash memory backup system and method

• US 8,041,879 B2
• Filed: 12/28/2005
• Issued: 10/18/2011
• Est. Priority Date: 02/18/2005
• Status: Active Grant

• Current Assignee: Western Digital Israel Limited (Western Digital Corporation)
• Original Assignee: SanDisk IL Ltd. (Western Digital Corporation)
• Inventors: Erez, Eran
• Primary Examiner(s): Shah; Sanjiv
• Assistant Examiner(s): DILLON, SAMUEL A
• Application Number:
  US11/318,863
• Publication Number:
  US 20060198202A1
• Time in Patent Office: 2,120 Days
• Field of Search: 711/103, 711/154, 711/161, 711/162, 714/6.2, 714/6.3, 714/6.32, 714/16
• US Class Current: 711/103
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory

Abstract

A flash memory system includes a flash controller for controlling operation of at least two flash memory devices. A page buffer is allocated within each flash memory device, such that one page buffer functions as a designated target buffer and another page buffer functions as a mirror buffer. The flash controller transmits the page data to two flash memory devices simultaneously, such that no backup of the page data is required to be kept in the flash controller. Hence, there is no delay in writing the next page data from a host computer to the flash controller.

Claims

1. A flash memory system comprising:

(a) at least two flash memory devices, each said flash memory device having at least one respective page buffer allocated therein as temporary storage area for data to be programmed in a first of said flash memory devices, the page buffer of a second of said flash memory devices acting as a backup copy for the data to be programmed in the first flash memory device; and

(b) a flash controller operative;

(i) to transmit data from an area designated for temporary storage of said controller both to the respective page buffer of the first said flash memory device and to the respective page buffer of the second said flash memory device, the transmitting of data further includes defining a page address within the first said flash memory device and the second said flash memory device to which the transmitted data is to be programmed;

(ii) to allocate the area designated for temporary storage of the data on said controller for other data upon successfully transmitting said data to the respective page buffer of first flash memory device and the respective page buffer of the second flash memory device;

(iii) subsequent to said transmitting, to program said data in said first flash memory device from said respective page buffer of said first flash memory device at the defined page address;

(iv) to check a programming failure of said programming of said data in said first flash memory device,

(v) in case of said programming failure in said first flash memory device, to program said data into said second flash memory device at the defined page address from said respective page buffer of said second flash memory device to which said data has been transmitted; and

(vi) to read data from said second flash memory device subsequent to programming said data into said second flash memory device,

wherein when the page address for the second flash memory device is already in use, a page address is pre-selected by the controller to be available for use in failure recovery.

2. The flash memory system of claim 1, wherein said controlling is implemented in software.

3. The flash memory system of claim 1, wherein said controlling is implemented in hardware.

4. The flash memory system of claim 1, wherein said controlling is implemented by a combination of software and hardware.

5. The flash memory system of claim 1, wherein said controller is operative to transmit said data in parallel to said respective page buffer of said first flash memory device and said respective page buffer of said second flash memory device.

6. The flash memory system of claim 1, wherein said controller is operative to transmit said data consecutively to said respective page buffer of said first flash memory device and said respective page buffer of said second flash memory device.

7. The flash memory system of claim 1, wherein said flash memory devices are NAND flash memory devices.

8. A method for managing a flash memory system, the method comprising the steps of, upon the system receiving an instruction from a host to store data, obeying the instruction by:

(a) transmitting data from a temporary storage of a controller of the flash memory system to a first respective page buffer allocated within a first flash memory device of the flash memory system;

(b) also transmitting said data from the temporary storage of the controller of the flash memory system to a second respective page buffer allocated within a second flash memory device of the flash memory system, wherein the first page buffer and the second page buffer act as temporary storage area for data to be programmed in the first flash memory device, the page buffer of the second flash memory device acting as a backup copy for said data to be programmed in the first flash memory device and wherein the transmitting of data includes defining a page address within the first flash memory device and the second flash memory device into which the transmitted data is to be programmed;

(c) allocating the temporary storage of the controller of the flash memory system that is used for transmitting the data to the respective page buffer of the first flash memory device and the respective page buffer of the second flash memory device for storing new data upon successfully transmitting the data from the temporary storage of the controller of the flash memory system to the respective page buffers of the first flash memory device and the second flash memory device;

(d) subsequent to said transmitting of said data to both said first and second page buffers, programming said data to a non-volatile memory of said first flash memory device at the defined page address;

(e) checking a programming failure of said programming of said data to said non-volatile memory of said first flash memory device;

(f) in case of said programming failure in said first flash memory device, programming said data to a non-volatile memory of said second flash memory device at the defined page address from said second respective page buffer; and

(g) subsequent to said programming of said data into said non-volatile memory of said second flash memory device, reading said data from said non-volatile memory of said second flash memory device,

wherein when the page address for the second flash memory device is already in use, a page address is pre-selected by the controller to be available for use in failure recovery.

9. The method of claim 8, wherein said steps of transmitting are carried out in parallel.

10. The method of claim 8, wherein said steps of transmitting are carried out consecutively.