Memory device with emulated characteristics

• US 8,041,881 B2
• Filed: 06/12/2007
• Issued: 10/18/2011
• Est. Priority Date: 07/31/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Wang, David T., Smith, Michael John Sebastian, Weber, Frederick Daniel, Schakel, Keith R., Rajan, Suresh Natarajan
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US11/762,010
• Publication Number:
  US 20080056014A1
• Time in Patent Office: 1,589 Days
• Field of Search: 711/103, 711/104, 711/105, 711/110
• US Class Current: 711/103
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number.

Claims

1. A memory apparatus for use with a host system, the memory apparatus comprising:

a plurality of memory circuits;

one or more first components of a first type, each of the one or more first components being electrically couplable to the host system; and

one or more second components of a second type different from the first type, each of the one or more second components being electrically couplable to the host system, the first and second components being operable to present to the host system a simulated memory circuit where there is a difference in at least one aspect between the simulated memory circuit and at least one of the plurality of memory circuits,

wherein each memory circuit of the plurality of memory circuits is electrically coupled to at least one of the one or more first components of the first type and to at least one of the one or more second components of the second type, where the one or more first components and the one or more second components are further operable to identify at least one of the plurality of memory circuits that is not being accessed and to perform a power-saving operation on the at least one of the plurality of memory circuits identified as not being accessed.

2. The memory apparatus of claim 1, where the one or more first components are operable to present a control interface between the host system and the plurality of memory circuits, and

the one or more second components are operable to present a data interface between the host system and the plurality of memory circuits.

3. The memory apparatus of claim 2, where the first type is a register and the second type is a buffer.

4. The memory apparatus of claim 2, where the control interface is configured to send and receive control, command and clock signals, and the data interface is configured to send and receive data signals.

5. The memory apparatus of claim 1, where the plurality of memory circuits comprise a stack of dynamic random access memory (DRAM) circuits and are coupled to a dual-inline memory module (DIMM).

6. The memory apparatus of claim 5, where the DIMM is a registered DIMM (R-DIMM).

7. The memory apparatus of claim 5, where the stack further includes the one or more second components of the second type.

8. The memory apparatus of claim 5, where the stack comprises a plurality of address, control and clock buses.

9. The memory apparatus of claim 5, where the stack comprises a single shared address, control and clock bus coupled to each of the plurality of memory circuits in the stack.

10. The memory apparatus of claim 5, where the stack comprises a shared data bus coupled to two or more of the plurality of memory circuits.

11. The memory apparatus of claim 5, where the stack comprises a plurality of data buses, each of the plurality of data buses being coupled to two or more of the plurality of memory circuits.

12. The memory apparatus of claim 5, where the stack comprises a plurality of data buses, each of the plurality of data buses being respectively coupled to a different one of the plurality of memory circuits.

13. The memory apparatus of claim 5, where the one or more second components are packaged separately from the plurality of memory circuits.

14. The memory apparatus of claim 5, where the one or more second components are packaged together with the plurality of memory circuits.

15. The memory apparatus of claim 1, where the power-saving operation comprises placing the at least one memory circuit identified as not being accessed in a precharge power down mode.

16. The memory apparatus of claim 15, where the one or more first components and the one or more second components are operable to place the at least one memory circuit identified as not being accessed in a precharge power down mode by controlling a clock enable input of the at least one identified memory circuit.

17. The memory apparatus of claim 1, where the one or more first components and the one or more second components are operable to identify the at least one of the plurality of memory circuits as not being accessed based on a number of open pages in at least one memory circuit of the plurality of memory circuits.

18. The memory apparatus of claim 1, where the one or more second components of the second type comply with a JEDEC standard and have forwarding, storing, or buffering capabilities.

19. The memory apparatus of claim 1, where the difference in at least one aspect comprises a signal difference where the signal is associated with a mode register operation.

20. The memory apparatus of claim 1, where the first and second components are electrically coupled to each of the memory circuits in a stack and where the stack includes a shared address, control and clock bus coupled to each of the plurality of memory circuits.

21. The memory apparatus of claim 1, where the difference in at least one aspect comprises a number of banks.

22. The memory apparatus of claim 21, where the plurality of memory circuits has eight banks and the simulated memory circuit has four banks or two banks.

23. The memory apparatus of claim 1, where the difference in at least one aspect includes a number of row-address signals.

24. The memory apparatus of claim 1, where the first components and second components are operable to perform the power saving operation by controlling a clock-enable pin of at least one of the plurality of memory circuits.

25. The memory apparatus of claim 1, where the first components and second components are further operable to select one or more of the plurality of memory circuits by generating one or more chip select signals and to perform an operation on the one or more selected memory circuits.