Faster memory access in non-unified memory access systems

• US 8,041,915 B1
• Filed: 06/11/2003
• Issued: 10/18/2011
• Est. Priority Date: 06/11/2003
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Devriendt, Paul, McGuire, Marlin L., Wahlig, Elsie D.
• Primary Examiner(s): PATEL, KAUSHIKKUMAR M
• Application Number:
  US10/459,344
• Time in Patent Office: 3,051 Days
• Field of Search: None
• US Class Current: 711/170
• CPC Class Codes: G06F 9/5016 the resource being the memory

Abstract

A generic NUMA-compliant memory selection technique is provided to enable a device capable of accessing memory anywhere in a system to select a near (potentially the nearest) memory for use with the device. For example, an AGP controller can access system memory anywhere within a multiprocessing node system, but will operate more efficiently, and interfere less with other data transactions, if it locates the closest memory, determines the memory addresses corresponding to the closest memory, and locks (or otherwise allocates) memory addresses for AGP functionality within the range of determined addresses in the near memory.

Claims

1. A method of near memory allocation for a device in an information processing system including a plurality of processing nodes and a plurality of memories respectively associated with the processing nodes, the method comprising:

determining a near processing node to the device;

determining a near memory associated with the near processing node;

allocating a portion of the near memory to the device;

wherein the determining the near processing node comprises;

accessing respective routing tables associated with each of the processing nodes and located in respective processing nodes;

processing information from the routing tables associated with respective ones of the processing nodes to determine which of the processing nodes is nearer to the device; and

selecting a specific one of the processing nodes which is nearer to the device as the near processing node.

2. The method of claim 1, wherein the determining a near memory associated with the near processing node comprises:

accessing a memory routing table associated with the near processing node; and

selecting from the memory routing table an address range corresponding to memory locations within the near memory.

3. The method of claim 1, wherein the allocating a portion of the near memory to the device comprises:

accessing a memory routing table in the near processing node; and

locking an address range within the near memory associated with the near processing node for use by the device.

4. The method of claim 1, wherein the determining a near memory associated with the near processing node comprises:

accessing a memory routing table in the near processing node;

selecting a memory address range which addresses memory locations locally associated with the near processing node; and

determining the near memory from the memory locations addressed by addresses within the memory address range.

5. The method of claim 4, wherein the allocating a portion of the near memory to the device comprises:

locking the address range within the near memory for use by the device.

6. The method of claim 1, wherein the allocating a portion of the near memory to the device comprises:

accessing a memory routing table in the near processing node; and

locking an address range within the near memory.

7. The method of claim 1 wherein determining a near processing node to the device further comprises determining a location of each processing node in relation to a bridge circuit.

8. The method of claim 1 wherein a device driver associated with the device is utilized to determine the near processing node.

9. An apparatus comprising:

at least one computer readable storage medium; and

near memory selector code encoded on the at least one computer readable storage medium, the near memory selector code including instructions for determining a near processing node which corresponds to a data path between a device and the near processing node which is shorter than another data path between the device and another processing node, and instructions for allocating memory locations in a near memory which is locally coupled to the near processing node, wherein each of the near processing node and the another processing node locally store associated topology information that is used to determine locations of the near processing node and the another processing node with respect to the device.

10. The apparatus of claim 9 further comprising:

a plurality of processing nodes including the near processing node; and

a plurality of memories including the near memory, each of the plurality of memories being locally coupled to one of the plurality of processing nodes and remotely accessible by others of the processing nodes, the near memory being locally coupled to the near processing node.

11. The apparatus of claim 10 further comprising:

the device coupled to at least one of the processing nodes, wherein the near memory selector code is comprised within a device driver corresponding to the device.

12. The apparatus of claim 11 wherein the device is an accelerated graphics port (AGP) controller, and the near memory selector code is comprised within an AGP driver.

13. The apparatus of claim 10 further comprising:

a SCSI device coupled to at least one of the processing nodes, wherein the near memory selector code is comprised within a SCSI device driver.

14. The apparatus of claim 10 wherein:

each of the processing nodes comprises a processor core; and

at least one of the processing nodes comprises an AGP controller, the AGP controller corresponding to an AGP driver including the near memory selector code.

15. The apparatus of claim 9 wherein the near memory selector code is executable to determine the near processing node based on a location of each processing node to a bridge circuit.

16. A near memory allocation computer program product, stored on at least one computer readable storage media, for configuring memory in an information processing system including a plurality of processing nodes, a plurality of memories associated with the processing nodes, and a device, the product comprising:

instructions for determining a near processing node to the device, wherein the

instructions for determining the near processing node to the device include,

instructions for accessing respective routing tables associated with respective ones of the processing nodes, the respective routing tables located in respective ones of the processing nodes,

instructions for processing information from the routing tables to determine which one of the processing nodes is nearer to the device; and

instructions for selecting the processing node which is nearer to the device as the near processing node;

instructions for determining a near memory associated with the near processing node; and

instructions for allocating a portion of the near memory to the device.

17. The computer program product of claim 16, wherein the instructions for determining a near memory associated with the near processing node comprise:

instructions for accessing a memory routing table associated with the near processing node; and

instructions for selecting from the memory routing table an address range corresponding to memory locations within the near memory.

18. The computer program product of claim 17, wherein the instructions for allocating a portion of the near memory to the device comprise:

instructions for accessing the memory routing table; and

instructions for locking the selected address range for use by the device.

19. The computer program product of claim 16, wherein the instructions for allocating a portion of the near memory to the device comprise:

instructions for accessing a memory routing table in the near processing node; and

instructions for locking an address range within the near memory for use by the device.

20. The computer program product of claim 16, wherein the instructions for determining a near memory associated with the near processing node comprise:

instructions for accessing a memory routing table in the near processing node;

instructions for selecting a memory address range which addresses memory locations locally associated with the near processing node; and

instructions for determining the near memory from the memory locations addressed by addresses within the memory address range.

21. The computer program product of claim 20, wherein the instructions for allocating a portion of the near memory to the device comprise:

instructions for accessing a memory routing table in the near processing node; and

instructions for locking the address range within the near memory for use by the device.

22. The computer program product of claim 16, wherein the instructions for allocating a portion of the near memory to the device comprise:

instructions for accessing a memory routing table in the near processing node; and

instructions for locking an address range within a memory associated with the near processing node.

23. The computer program product of claim 16 wherein the computer program product is a device driver.

24. The computer program product of claim 16, wherein the instructions for determining the near processing node to the device are included within a device driver associated with the device.

25. A method of near memory allocation for a device in an information processing system including a plurality of processor nodes and a plurality of memories respectively associated with the processor nodes, the method comprising:

accessing respective routing tables in each of the processing nodes;

determining, based on accessing the routing tables in each of the processing nodes, a nearest processing node to a bridge device as a near processing node;

accessing a memory routing table in the near processing node and determining therefrom an address range associated with a near memory associated with the near processing node; and

allocating device memory in the near memory within the address range to the device.