Random signal generator

• US 8,041,950 B2
• Filed: 03/25/2010
• Issued: 10/18/2011
• Est. Priority Date: 11/28/2000
• Status: Expired due to Term

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Marinet, Fabrice, Malherbe, Alexandre
• Primary Examiner(s): REVAK, CHRISTOPHER A
• Application Number:
  US12/731,808
• Publication Number:
  US 20100180117A1
• Time in Patent Office: 572 Days
• Field of Search: None
• US Class Current: 713/168
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes
• CPC Class Codes: G06K 19/073 Special arrangements for circuits, e.g. for protecting identification code in memory protection against unauthorised use of computer memory G06F12/14
• CPC Class Codes: G06K 19/07363 by preventing analysis of the circuit, e.g. dynamic or static power analysis or current analysis
• CPC Class Codes: H03K 3/84 Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators

Abstract

A random signal generator uses a folded MOS transistor, whose drain-source current includes a random component, as an electronic noise source. The random signal generator generates a random binary signal from the random component. The invention may be applied, in particular, to smart cards.

Claims

1. An electronic device comprising:

at least one random signal generator circuit configured to generate a random digital number and comprising

an electronic noise source comprising a folded MOS transistor having a drain-source current with a random component, and

a logic circuit configured to generate the random digital number based upon the random component;

a communications module coupled to said at least one random signal generator circuit and configured to transmit the random digital number to an external terminal; and

a processor coupled to said at least one random signal generator circuit and configured to transform the generated random digital number based upon an authentication function that uses a secret key;

said processor also configured to compare a result of the authentication function to a result of another authentication function provided by the external terminal in response to the random digital number being sent thereto, and to authorize a transaction with the external terminal if the comparison is a match.

2. An electronic device according to claim 1, wherein said at least one random signal generator circuit, communications module, and processor are configured in an integrated circuit.

3. An electronic device according to claim 2, further comprising a chip card substrate carrying said integrated circuit.

4. An electronic device according to claim 1, wherein said at least one random signal generator circuit comprises a plurality thereof.

5. An electronic device according to claim 1, wherein the electronic device comprises a portable electronic device.

6. An electronic device according to claim 1, wherein said folded MOS transistor comprises a drain and a source with a channel defined therebetween, with the channel being S-shaped and having a size that is at a resolution limit based upon manufacturing technology.

7. An electronic device according to claim 1, wherein said folded MOS transistor comprises a drain and a source with a channel defined therebetween, with the channel being zigzag-shaped and having a size that is at a resolution limit based upon manufacturing technology.

8. An electronic device according to claim 1, further comprising a reference transistor coupled to said folded MOS transistor, said reference transistor configured to receive a gate voltage and a bias current equal to a gate voltage and a bias current applied to said folded MOS transistor for causing the drain-source current therefrom to randomly vary.

9. An electronic device according to claim 8, further comprising a comparison circuit configured to compare the randomly varying drain-source current to a detection current.

10. An electronic device according to claim 9, wherein said comparison circuit is configured to determine a difference between the randomly varying drain-source current and the detection current;

and further comprising an amplifier configured to amplify the difference.

11. An electronic device according to claim 1, wherein said logic circuit comprises a sampling circuit configured to sample the digital signal for providing the random digital number.

12. An electronic device according to claim 1, further comprising a circuit configured to maintain a gate voltage on said folded MOS transistor within a desired range of values.

13. An electronic device comprising:

at least one random signal generator circuit configured to generate a random number and comprising

a folded MOS transistor with a random component, and

a logic circuit configured to generate the random number based upon the random component;

a communications module coupled to said at least one random signal generator circuit and configured to transmit the random number to an external terminal; and

a processor coupled to said at least one random signal generator circuit and configured to transform the generated random number based upon an authentication function that uses a secret key;

said processor also configured to compare a result of the authentication function to a result of another authentication function provided by the external terminal in response to the random number being sent thereto.

14. An electronic device according to claim 13, wherein said at least one random signal generator circuit, communications module, and processor are configured in an integrated circuit.

15. An electronic device according to claim 14, further comprising a chip card substrate carrying said integrated circuit.

16. An electronic device according to claim 13, wherein said at least one random signal generator circuit comprises a plurality thereof.

17. An electronic device according to claim 13, wherein said folded MOS transistor comprises a drain and a source with a channel defined therebetween, with the channel being S-shaped and having a size that is at a resolution limit based upon manufacturing technology.

18. An electronic device according to claim 13, wherein said folded MOS transistor comprises a drain and a source with a channel defined therebetween, with the channel being zigzag-shaped and having a size that is at a resolution limit based upon manufacturing technology.

19. An electronic device according to claim 13, further comprising a reference transistor coupled to said folded MOS transistor, said reference transistor configured to receive a gate voltage and a bias current equal to a gate voltage and a bias current applied to said folded MOS transistor for causing a drain-source current therefrom to randomly vary.

20. A method of authorizing a transaction with an external terminal using an electronic device comprising at least one random signal generator circuit configured to generate a random number and comprising a folded MOS transistor with a random component, and a logic circuit configured to generate the random number based upon the random component, the method comprising:

using a communications module coupled to the at least one random signal generator circuit to transmit the random number to the external terminal;

using a processor coupled to the at least one random signal generator circuit to transform the generated random number based upon an authentication function that uses a secret key; and

also using the processor to compare a result of the authentication function to a result of another authentication function provided by the external terminal in response to the random number being sent thereto, and to authorize the transaction with the external terminal if the comparison is a match.

21. A method according to claim 20, wherein the at least one random signal generator circuit, communications module, and processor are configured in an integrated circuit.

22. A method according to claim 21, further comprising a chip card substrate carrying the integrated circuit.

23. A method according to claim 20, wherein the folded MOS transistor comprises a drain and a source with a channel defined therebetween, with the channel being S-shaped and having a size that is at a resolution limit based upon manufacturing technology.

24. A method according to claim 20, wherein the folded MOS transistor comprises a drain and a source with a channel defined therebetween, with the channel being zigzag-shaped and having a size that is at a resolution limit based upon manufacturing technology.