Input compensated and/or overcompensated computing

• US 8,041,992 B2
• Filed: 05/11/2009
• Issued: 10/18/2011
• Est. Priority Date: 05/11/2009
• Status: Active Grant

• Current Assignee: Empire Technology Development LLC (Allied Inventors Management, LLC)
• Original Assignee: Technology Currents LLC (Intellectual Ventures LLC)
• Inventors: Potkonjak, Miodrag
• Primary Examiner(s): BONZO, BRYCE P
• Application Number:
  US12/463,982
• Publication Number:
  US 20100287404A1
• Time in Patent Office: 890 Days
• Field of Search: 714/10
• US Class Current: 714/10
• CPC Class Codes: G06F 11/0721 within a central processing unit [CPU]
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40

Abstract

Techniques are generally described for correcting computation errors via input compensation and/or input overcompensation. In various examples, errors of a computation may be detected, and input compensation and/or overcompensation to correct the errors may be created. The disclosed techniques may be used for power and/or energy minimization/reduction, and debugging, among other applications. Other embodiments and/or applications may be disclosed and/or claimed.

Claims

1. A method for performing a computation on a computing platform, the method comprising:

associating by the computing platform an arithmetic compensation or overcompensation with an arithmetic input to the computation, the arithmetic compensation or overcompensation to be used computationally in conjunction with the arithmetic input in performing the computation on the computing platform to at least reduce an error of the computation; and

performing by the computing platform, the computation using the arithmetic input and computationally, the arithmetic compensation or overcompensation.

2. The method of claim 1, further comprising

detecting the error, by the computing platform, based at least in part on a prior performing of the computation on the computing platform;

and

determining by the computing platform, the arithmetic compensation or overcompensation to be associated with the arithmetic input to at least reduce the detected error when performing the computation on the computing platform.

3. The method of claim 2, further comprising repeating the detecting and determining by the computing platform when a design metric for the computing platform has not been achieved or a repetition limit has not been reached, wherein the design metric comprises a selected one of an energy usage or a speed of execution of the computing platform.

4. The method of claim 2, wherein the computing platform has an energy usage design metric, and wherein detecting and determining are performed by the computing platform for a selected pair of supply and threshold voltages for the computing platform.

5. The method of claim 4 further comprising estimating by the computing platform an amount of energy required by the computing platform to employ the arithmetic compensation or overcompensation to the arithmetic input when performing the computation.

6. The method claim 5, wherein estimating comprises performing statistical analysis or simulation by the computing platform.

7. The method of claim 2, wherein detecting comprises detecting by the computing platform, a transitive or non-permanent error.

8. The method of claim 2, wherein determining comprises determining by the computing platform, an arithmetic compensation or overcompensation to the arithmetic input to eliminate the detected error.

9. The method of claim 1, further comprising

sending a result of the prior performing of the computation, by the computing platform, to another computing platform to at least detect the error, by the other computing platform, based at least in part on the prior performing of the computation on the computing platform.

10. The method of claim 9, further comprising

receiving by the computing platform, from the other or a third computing platform, the arithmetic compensation or overcompensation to be associated with the arithmetic input to at least reduce the detected error when performing the computation on the computing platform.

11. The method of claim 1 wherein performing comprises applying the arithmetic compensation or overcompensation to the arithmetic input prior to providing the arithmetic input to the computation.

12. A method for a computing platform to at least reduce an error of a computation performed on a target computing platform, the method comprising:

detecting by the computing platform, the error of the computation performed on the target computing platform; and

determining and providing by the computing platform to the target computation, an arithmetic compensation or overcompensation to an arithmetic input to the computation to at least reduce the error when the computation is performed on the target computing platform.

13. The method of claim 12, further comprising receiving by the computing platform, a result of a prior performing of the computation on the target computing platform.

14. The method of claim 12, further comprising performing or modeling by the computing platform, the computation to be performed by the target computing platform.

15. The method of claim 12, further comprising repeating the detecting and determining by the computing platform when a design metric for the computing platform has not been achieved or a repetition limit has not been reached, wherein the design metric comprises a selected one of an energy usage or a speed of execution of the target computing platform.

16. A method for a computing platform to correct or partially correct an error of a computation performed on a target computing platform, the method comprising:

receiving by the computing platform, from another computing platform, a description of the error of the computation performed on the target computing platform; and

determining and providing by the computing platform to the target computation, an arithmetic compensation or overcompensation to an arithmetic input to the computation to correct or partially correct the error when the computation is performed on the target computing platform.

17. The method of claim 16, further comprising repeating the receiving and determining by the computing platform when a design metric for the computing platform has not been achieved or a repetition limit has not been reached, wherein the design metric comprises a selected one of an energy usage or a speed of execution of the target computing platform.

18. An apparatus for performing a computation, the apparatus comprising:

a processor configured to execute instructions;

a storage medium coupled to the processor, and having stored therein instructions to be executed by the processor, wherein when executed, the instructions enable the apparatus to

associate an arithmetic compensation or overcompensation with an arithmetic input to a computation, the arithmetic compensation or overcompensation to be used in conjunction with the arithmetic input when performing the computation on the computing apparatus to at least reduce an error of the computation; and

perform the computation using the arithmetic input in conjunction with the arithmetic compensation or overcompensation.

19. The computing apparatus of claim 18, wherein the instructions further enable the apparatus to

detect the error based at least in part on a prior performing of the computation on the computing apparatus;

and

determine the arithmetic compensation or overcompensation to be associated with the arithmetic input to at least reduce the detected error when performing the computation on the computing apparatus.

20. The computing apparatus of claim 18, wherein the instructions further enable the apparatus to repeat the detect and determine when a design metric for the computing apparatus has not been achieved or a repetition limit has not been reached, wherein the design metric comprises a selected one of an energy usage or a speed of execution of the computing platform.

21. An apparatus for at least reducing an error of a computation performed on a target computing platform, the apparatus comprising:

a processor configured to execute instructions;

a storage medium coupled to the processor, and having stored therein instructions to be executed by the processor, wherein when executed, the instructions enable the apparatus to

detect an error of a computation performed on the target computing platform; and

determine and provide to the target computation platform, an arithmetic compensation or overcompensation to an arithmetic input to the computation to at least reduce the error when the computation is performed on the target computing platform.

22. The computing apparatus of claim 21, wherein the instructions further enable the apparatus to repeat the detect and determine when a design metric for the target computing platform has not been achieved or a repetition limit has not been reached, wherein the design metric comprises a selected one of an energy usage or a speed of execution of the target computing platform.

23. An apparatus for at least reducing an error of a computation performed on a target computing platform, the apparatus comprising:

a processor configured to execute instructions;

a storage medium coupled to the processor, and having stored therein instructions to be executed by the processor, wherein when executed, the instructions enable the apparatus to

receive from another computing platform, a description of the error of the computation performed on the target computing platform; and

determine and provide to the target computation, an arithmetic compensation or overcompensation to an arithmetic input to the computation to correct or partially correct the error when the computation is performed on the target computing platform.

24. The apparatus of claim 23, wherein the instructions further enable the apparatus to repeat the receive and determine when a design metric for the target computing platform has not been achieved or a repetition limit has not been reached, wherein the design metric comprises a selected one of an energy usage or a speed of execution of the target computing platform.

25. An article of manufacture comprising:

a computer readable storage medium; and

a plurality of instructions stored in the storage medium, wherein the instructions are designed to be executed by a processor of an apparatus to enable the apparatus to determine and provide to a target computation platform an arithmetic compensation or overcompensation to an arithmetic input to a computation to at least reduce an error of the computation when the computation is performed on the target computing platform.

26. The article of claim 25, wherein the instructions further enable the apparatus to detect an error of the computation when performed on the target computing platform.

27. The article of claim 26, wherein the instructions further enable the apparatus to repeat the detect and determine when a design metric for the target computing platform has not been achieved or a repetition limit has not been reached, wherein the design metric comprises a selected one of an energy usage or a speed of execution of the target computing platform.

28. The article of claim 25, wherein the apparatus comprises the target computing platform.