Three dimensional memory in a system on a chip

• US 8,042,082 B2
• Filed: 09/12/2008
• Issued: 10/18/2011
• Est. Priority Date: 09/12/2007
• Status: Expired due to Fees

• Current Assignee: Neal Solomon
• Original Assignee: Neal Solomon
• Inventors: Solomon, Neal
• Primary Examiner(s): DOAN, NGHIA M
• Application Number:
  US12/283,455
• Publication Number:
  US 20090070721A1
• Time in Patent Office: 1,131 Days
• Field of Search: 716100-105, 716116-119, 716/138, 365129-131
• US Class Current: 716/116
• CPC Class Codes: G06F 2115/06 Structured ASICs
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices

Abstract

The invention relates to multi-planar memory components in a three-dimensional integrated circuit system configuration. A multi-planar memory system consisting of a plurality of memory circuit planes in a three-dimensional system on a chip (3D SoC) comprised of a plurality of memory layers, at least one logic circuit layer and an interface configured to provide access to memory and logic circuit layers.

Claims

1. A multi-planar memory system consisting of a plurality of memory circuit planes in a three dimensional (3D) stem on a chip (SoC) with through silicon vias (TSVs) comprised of:

a multi-circuit set of memory circuit layers arranged in a 3D configuration;

a plurality of memory circuit layers, each layer of which includes memory circuit component types;

at least one logic circuit layer connected to the memory circuit layers by TSVs;

wherein the types of memory on memory circuit layers are used by at least one logic circuit layer, which are configured to access at least one memory type on each memory circuit layer using the TSVs;

wherein when at least one memory type on a memory circuit layer is sandwiched between at least two logic circuit layers, the memory types on the memory circuit layers are connected with TSVs; and

wherein the memory circuit layers store data and instructions.

2. The multi-planar memory system of claim 1, wherein:

the memory circuits are on at least two layers of the multi-planar memory system;

the memory circuits are configured on at least one tile on a layer of the multi-planar memory system; and

interconnection between at least two memory tiles on a plurality of layers of the multi-planar memory system are connected by TSVs.

3. The multi-planar memory system of claim 2, wherein:

the configuration of data and instructions stored in specific memory circuits in the multi-planar memory system are rearranged by reassigning the data and instructions to different memory components on at least one tile on a layer of the multi-layer of the multi-planar memory system; and

the data and instructions are tagged and tracked in databases in order to identify the storage locations in the multi-planar memory system.

4. The multi-planar memory system of claim 2, wherein:

the multi-planar memory system uses multiple pipelines to store and access data and instructions in the memory components simultaneously in at least two tiles.

5. The multi-planar memory system of claim 2, wherein:

The data are transferred between multiple memory tiles in the multi-planar memory system simultaneously.

6. The multi-planar memory system of claim 2, wherein:

data and instructions are transferred between tiles on different layers of a multi-planar memory system by using TSVs.

7. The multi-planar memory system of claim 1, wherein:

the memory circuit layers are accessed by logic circuits on at least one layers in the multi-planar memory system using the TSVs.

8. The multi-planar memory system of claim 1, wherein:

when the system accesses data or instructions in two or more memory circuits in the multi-planar memory system, the order of the sequence of processing data or instructions changes in different logic applications.

9. The multi-planar memory system of claim 1, wherein:

the logic circuit is a microprocessor, an FPGA, an ASIC or an SoC.

10. The multi-planar memory system of claim 1, wherein:

the data are pre-fetched to allocate to specific memory circuits on layers of the multi-planar memory system by anticipating the configuration of reconfigurable logic components for different application types.

11. The multi-planar memory system of claim 1, wherein:

multiple pipelines are simultaneously active to store data or instructions in memory circuitry on at least one layer of the 3D SoC.

13. The multi-planar memory system of claim 8, wherein:

the logic circuit is a microprocessor, an FPGA an ASIC or a SoC.

12. A multi-planar memory system consisting of a plurality of memory circuit planes in three dimensional (3D) system on a chip (SoC) with through silicon vias (TSVs) comprised of:

a multi-circuit set of memory circuit layers arranged in a 3D configuration;

a plurality of memory circuit layers, each layer of which includes memory circuit component types;

at least one logic circuit layer configured to access at least one memory circuit layer by TSVs;

wherein the types of memory in the memory circuit layers are used by at least one logic circuit layer, which are configured to access at least one memory type on each memory circuit layer using the TSVs;

wherein when at least one memory type on a memory circuit layer is sandwiched between at least two logic circuit layers, the memory types on the memory circuit layers are connected with TSVs;

wherein at least one logic circuit layer accesses different memory types on the memory circuit layers in the 3D SoC simultaneously; and

wherein the memory circuit layers store data and instructions.

14. The multi-planar memory system of claim 12, wherein:

data are tagged for identification in a 3D SoC;

data tags update a central database;

when the system engages in a reconfiguration of its evolvable hardware, the data reorganize their configuration in the memory circuits on at least one layer in the multi-planar memory system with new data tags that refer to new data locations; and

the database is updated with new locations of data in the multi-planar memory system.

15. A multi-planar memory system consisting of a plurality of memory circuit planes in a three dimensional (3D) memory module with through silicon vias (TSVs) comprised of:

a multi-circuit set of memory circuit layers arranged in a 3D configuration;

a plurality of memory circuit layers, each layer of which includes memory circuit component types;

at least one logic circuit configured to access and control at least one memory circuit, such logic circuit on at least one tile of a layer of the multi-layer memory system;

wherein the multi-planar memory system is configured as a set of memory types on memory circuit layers in an integrated memory module connected with TSVs;

wherein at least one logic circuit on a tile on one layer in the 3D memory module accesses data and instructions from the memory types in at least one memory circuit layer using the TSVs; and

wherein the memory circuits on at least one layer of the 3D memory module store data and instructions.

16. The multi-planar memory system of claim 15, wherein:

the at least one logic circuit is a microprocessor, FPGA, ASIC or SoC.

17. The multi-planar memory system of claim 15, wherein:

at least one memory circuit layer on the 3D memory module is accessed simultaneously by at least two logic circuits.

18. The multi-planar memory system of claim 15, wherein:

data and instructions are processed in at least two memory circuit layers of the 3D memory module using parallel pipelines.

19. The multi-planar memory system of claim 15, wherein:

when data are processed on two or more logic circuit tiles, multiple pipelines are used to store and access data and instructions on different memory circuits in a plurality of layers of the 3D memory module.

20. The multi-planar memory system of claim 15, wherein:

the dynamics of data storage continually shift in the 3D memory module by using at least one memory circuit layer;

the at least one logic circuit controls the data reconfiguration process in at least one memory circuit layer in the 3D memory module; and

patterns of data flows in the 3D memory module are modulated by the at least one logic circuit.