Method of fabricating stacked assembly including plurality of stacked microelectronic elements
First Claim
1. A method of fabricating a stacked assembly including a plurality of stacked microelectronic elements, comprising:
- a) providing first and second microelectronic substrates each including a plurality of microelectronic elements attached together at dicing lanes, each of said plurality of microelectronic elements including a first edge and a second edge remote from said first edge, each of said plurality of microelectronic elements further including contacts and traces extending from said contacts to identical locations proximate said first and second edges;
b) stacking and joining said first and second microelectronic substrates in first and second different orientations to form a stacked assembly such that said first edges of said microelectronic elements of said first microelectronic substrate are aligned with said second edges of said microelectronic elements of said second microelectronic substrate;
c) exposing said traces at said first and second edges of said microelectronic elements of said first and second microelectronic substrates, respectively; and
d) forming first and second leads, said first leads connected to said exposed traces of said microelectronic elements of said first microelectronic substrate, said second leads connected to said exposed traces of said microelectronic elements of said second microelectronic substrate, said second leads being electrically isolated from said first leads.
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Abstract
A method is provided for fabricating a stacked microelectronic assembly by steps including stacking and joining first and second like microelectronic substrates, each including a plurality of like microelectronic elements attached together at dicing lanes. Each microelectronic element has boundaries defined by edges including a first edge and a second edge. The first and second microelectronic substrates can be joined in different orientations, such that first edges of microelectronic elements of the first microelectronic substrate are aligned with second edges of microelectronic elements of the second microelectronic substrate. After exposing traces at the first and second edges of the microelectronic elements of the stacked microelectronic substrates, first and second leads can be formed which are connected to the exposed traces of the first and second microelectronic substrates, respectively. The second leads can be electrically isolated from the first leads.
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Citations
16 Claims
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1. A method of fabricating a stacked assembly including a plurality of stacked microelectronic elements, comprising:
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a) providing first and second microelectronic substrates each including a plurality of microelectronic elements attached together at dicing lanes, each of said plurality of microelectronic elements including a first edge and a second edge remote from said first edge, each of said plurality of microelectronic elements further including contacts and traces extending from said contacts to identical locations proximate said first and second edges; b) stacking and joining said first and second microelectronic substrates in first and second different orientations to form a stacked assembly such that said first edges of said microelectronic elements of said first microelectronic substrate are aligned with said second edges of said microelectronic elements of said second microelectronic substrate; c) exposing said traces at said first and second edges of said microelectronic elements of said first and second microelectronic substrates, respectively; and d) forming first and second leads, said first leads connected to said exposed traces of said microelectronic elements of said first microelectronic substrate, said second leads connected to said exposed traces of said microelectronic elements of said second microelectronic substrate, said second leads being electrically isolated from said first leads. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of fabricating a stacked assembly including a plurality of stacked microelectronic elements, comprising:
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a) providing a plurality of microelectronic substrates, each said microelectronic substrate including a plurality of like microelectronic elements each having a face and first and second edges extending away from said face, each of said microelectronic elements having contacts at said face and traces extending along said face from said contacts to locations proximate said first and second edges, said traces of each said microelectronic element extending in a lengthwise direction and being spaced apart in a lateral direction, transverse to said lengthwise direction; b) stacking and joining said plurality of microelectronic substrates in different orientations such that said first edges of said microelectronic elements of a first one of said microelectronic substrates are aligned with corresponding second edges of said microelectronic elements of each other of said plurality of stacked and joined microelectronic substrates and each of said traces of said microelectronic elements of said first microelectronic substrate at said first edges is spaced laterally from each of said traces of said microelectronic elements of any other of said stacked and joined microelectronic substrates. - View Dependent Claims (12, 13, 14, 15)
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16. A method of fabricating a stacked assembly including a plurality of stacked microelectronic elements, comprising:
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a) providing a plurality of microelectronic substrates, each of said microelectronic substrates including a plurality of microelectronic elements attached together at edges defined by dicing lanes, said edges including first and second edges, each of said microelectronic elements having a face extending between said first and second edges, each said microelectronic substrate having bond pads at said face and redistribution traces extending along said face from said bond pads towards said first and second edges, said redistribution traces of each said microelectronic substrate having a pitch, said pitch being greater than a number N multiplied by a width of said redistribution traces at said first edge, N being greater than two, said redistribution traces at said first edge being offset from said redistribution traces at said second edge in a direction of said pitch of said redistribution traces; b) stacking a second one of said microelectronic substrates in a first orientation onto a first one of said microelectronic substrates in a second orientation such that said redistribution traces at said first edge of each microelectronic element of said first microelectronic substrate are offset from said redistribution traces of each corresponding microelectronic element of said second microelectronic substrate directly overlying said microelectronic element of said first microelectronic substrate; c) forming leads connected to said redistribution traces, said leads extending about said first and second edges of said microelectronic elements of said first and second microelectronic substrates; and d) dicing said stacked first and second microelectronic substrates along said dicing lanes into individual stacked assemblies having first and second edges, wherein closest adjacent leads at said first edges are laterally spaced from each other.
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Specification