Method of forming trench-gate field effect transistors

• US 8,043,913 B2
• Filed: 03/29/2011
• Issued: 10/25/2011
• Est. Priority Date: 05/26/2005
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Probst, Dean E., Yilmaz, Hamza, Kocon, Christopher Boguslaw, Calafut, Daniel, Yedinak, Joseph A., Marchant, Bruce D., Dolny, Gary M., Sapp, Steven P., Kraft, Nathan L., Grebs, Thomas E., Ridley, Rodney S.
• Primary Examiner(s): PHAM, THANHHA S
• Application Number:
  US13/075,091
• Publication Number:
  US 20110177662A1
• Time in Patent Office: 210 Days
• Field of Search: 438/259, 438270-271, 438/283, 438/589, 257/E21.655
• US Class Current: 438/259
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A method of forming a field effect transistor includes: forming a trench in a semiconductor region; forming a shield electrode in the trench; performing an angled sidewall implant of impurities of the first conductivity type to form a channel enhancement region adjacent the trench; forming a body region of a second conductivity type in the semiconductor region; and forming a source region of the first conductivity type in the body region, the source region and an interface between the body region and the semiconductor region defining a channel region therebetween, the channel region extending along the trench sidewall. The channel enhancement region partially extends into a lower portion of the channel region to thereby reduce a resistance of the channel region.

Claims

1. A method of forming a field effect transistor, comprising:

forming a trench in a semiconductor region;

forming a shield electrode in the trench;

performing an angled sidewall implant of impurities of the first conductivity type to form a channel enhancement region adjacent the trench;

forming a body region of a second conductivity type in the semiconductor region; and

forming a source region of the first conductivity type in the body region, the source region and an interface between the body region and the semiconductor region defining a channel region therebetween, the channel region extending along the trench sidewall,

wherein the channel enhancement region partially extends into a lower portion of the channel region to thereby reduce a resistance of the channel region.

2. The method of claim 1 further comprising forming a gate electrode over but insulated from the shield electrode.

3. The method of claim 2 wherein the channel enhancement region overlaps with the gate electrode along the trench sidewall.

4. The method of claim 1 wherein the channel enhancement region is self-aligned to the shield electrode.

5. The method of claim 1 wherein the semiconductor region includes a drift region of the second conductivity type extending over a substrate.

6. The method of claim 5 wherein the trench extends through the drift region and terminates within the substrate.

7. The method of claim 5 wherein the channel enhancement region partially extends into the body region and partially extends into the drift region.

8. The method of claim 1 wherein the semiconductor region includes a drift region of the second conductivity type extending over a substrate, and the shield electrode vertically overlaps the drift region and the substrate.

9. The method of claim 1 further comprising:

forming a screen oxide along the upper trench sidewalls prior to performing the angled sidewall implant.

10. A method of forming a shielded gate field effect transistor, comprising:

forming trenches in a semiconductor region;

forming a shield electrode in each trench, the shield electrode being insulated from the semiconductor region;

performing angled sidewall implants of impurities of the first conductivity type to form channel enhancement regions adjacent each trench along opposing sidewalls of each trench;

forming a body region of a second conductivity type in the semiconductor region; and

forming source regions of the first conductivity type in the body region, each source region and an interface between the body region and the semiconductor region defining a channel region therebetween, the channel region extending along the corresponding trench sidewall,

wherein each channel enhancement region partially extends into a lower portion of the corresponding channel region to thereby reduce a resistance of the channel region.

11. The method of claim 10 further comprising forming a gate electrode in each trench over but insulated from the shield electrode.

12. The method of claim 11 wherein channel enhancement regions overlap with corresponding gate electrodes along corresponding trench sidewalls.

13. The method of claim 10 wherein the channel enhancement regions are self-aligned to corresponding shield electrodes.

14. The method of claim 10 wherein the semiconductor region includes a drift region of the second conductivity type extending over a substrate.

15. The method of claim 14 wherein the trenches extend through the drift region and terminate within the substrate.

16. The method of claim 14 wherein the channel enhancement regions partially extend into the body region and partially extend into the drift region.

17. The method of claim 10 wherein the semiconductor region includes a drift region of the second conductivity type extending over a substrate, and the shield electrode in each trench vertically overlaps the drift region and the substrate.

18. The method of claim 10 further comprising:

forming a screen oxide along upper sidewalls of each trench prior to performing the angled sidewall implants.