finFETS and methods of making same

• US 8,043,920 B2
• Filed: 09/17/2009
• Issued: 10/25/2011
• Est. Priority Date: 09/17/2009
• Status: Active Grant

• Current Assignee: Auriga Innovations, Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: Li, Jinghong, Wang, Xinhui, Ouyang, Christine Qiqing, Chan, Kevin K., Yin, Haizhou, Kanarsky, Thomas Safron, Ren, Zhibin, Park, Dae-Gyu
• Primary Examiner(s): Stark; Jarrett
• Assistant Examiner(s): TOBERGTE, NICHOLAS J
• Application Number:
  US12/561,606
• Publication Number:
  US 20110062518A1
• Time in Patent Office: 768 Days
• Field of Search: 257/347, 257/401, 438/197, 438/300
• US Class Current: 438/300
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of fabricating and a structure of a merged multi-fin finFET. The method includes forming single-crystal silicon fins from the silicon layer of an SOI substrate having a very thin buried oxide layer and merging the end regions of the fins by growing vertical epitaxial silicon from the substrate and horizontal epitaxial silicon from ends of the fins such that vertical epitaxial silicon growth predominates.

Claims

1. A method, comprising:

(a) forming two or more silicon fins on a top surface of an insulating layer on a silicon substrate, each fin of said two or more fins having a central region between and abutting first and second end regions and opposite sides;

(b) forming a gate dielectric layer on said opposite sides of each fin of said two or more fins;

(c) forming an electrically conductive gate over said gate dielectric layer over said central region of each fin of said of two or more fins;

(d) removing said gate dielectric layer from said first and second end regions of each fin of said two or more fin and removing said end regions of each of said two or more fins to form exposed opposite first and second ends of said central regions of each fin of said two or more fins;

after (d), (e) removing said insulating layer to expose first and second regions of said substrate on opposite sides of said gate; and

after (e), (f) simultaneously growing epitaxial silicon from said first and second regions of said substrate and from said first and second ends of said central regions of each fin of said two or more fins to form respective first and second merged source/drains.

2. The method of claim 1, wherein said insulating layer has a thickness between about 20 nm and about 40 nm.

3. The method of claim 1, wherein in (e) surfaces of said first and second regions of said substrate are coplanar with a {100} plane of said substrate and said first and second ends of said each fin of said two or more fins are coplanar with a {110} plane of each fin of said two or more fins.

4. The method of claim 1, wherein (a) includes:

providing a silicon-on insulator wafer comprising a silicon layer, separated from said silicon substrate by said insulating layer, said insulating layer comprising silicon oxide; and

patterning said silicon layer into said two or more fins.

5. The method of claim 1, further including:

between (a) and (b) forming a dielectric cap on top surfaces of each fin of said two or more fins;

wherein (b) includes forming said gate dielectric layer on said dielectric cap; and

wherein (d) includes removing said dielectric cap from said first and second end regions of each fin of said two or more fins.

6. The method of claim 5, further including:

between (e) and (f), forming a first and second P-wells or N-wells in said first and second regions of said substrate; and

after said forming said first and second P-wells or said N-wells and after (f), ion implanting a dopant species into said first and second merged source/drains.

7. The method of claim 1, further including:

between (b) and (c), forming an electrically conductive depletion stop layer on said gate dielectric layer; and

(d) further includes removing said depletion stop layer from said first and second end regions of each fin of said two or more fins.

8. The method of claim 1, further including:

between (e) and (f), forming a first and second P-wells or N-wells in said first and second regions of said substrate.

9. The method of claim 1, further including:

after (f), ion implanting a dopant species into said first and second merged source/drains.

10. The method of claim 1, further including:

between (a) and (b), forming a recess part way through said insulating layer adjacent to said sides of each fin of said two or more fins.

11. The method of claim 1, wherein said first and second regions of said substrate include recesses part way through said substrate, said recesses formed adjacent to said sides of insulating layer in (d).

12. The method of claim 1, further including:

between (d) and (e), forming a conformal dielectric epitaxial stop layer on said first and second end regions of each fin of said two or more fins and regions of said insulating layer adjacent to said sides of each fin of said two or more fins in said first and second end regions and over regions of said substrate away from said two or more fins;

forming a conformal dielectric spacer layer on said stop layer; and

selectively removing said stop layer and said spacer layer from said first and second end regions of each fin of said two or more fins and regions of said insulating layer adjacent to said sides of each fin of said two or more fins in said first and second end regions, regions of said stop layer and said spacer layer remaining over said regions of said substrate away from said two or more fins.