Semiconductor device, method for manufacturing semiconductor device and apparatus for manufacturing semiconductor

• US 8,043,957 B2
• Filed: 05/16/2007
• Issued: 10/25/2011
• Est. Priority Date: 05/17/2006
• Status: Active Grant

• Current Assignee: Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
• Original Assignee: NEC Corporation
• Inventors: Yamamoto, Hironori, Tada, Munehiro, Hayashi, Yoshihiro, Ohtake, Hiroto, Ito, Fuminori
• Primary Examiner(s): VU, HUNG K
• Application Number:
  US12/299,375
• Publication Number:
  US 20090267198A1
• Time in Patent Office: 1,623 Days
• Field of Search: 438/622, 438/623, 438/624, 438/639, 438/687, 257/E21.261, 257/E21.575
• US Class Current: 438/622
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02216 the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/31633 Deposition of carbon doped silicon oxide, e.g. SiOC
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention provides a multilayer wiring technology by which high adhesiveness and high insulation reliability between wirings are obtained, while maintaining effective low capacitance between wirings. A semiconductor device is characterized in that a first insulating film is an insulating film formed of at least one layer which contains a siloxane structure containing silicon, oxygen and carbon; the siloxane structure in the inner part of the first insulating film contains a larger number of carbon atoms than the number of silicon atoms; and a modified layer which containing a smaller number of carbon atoms and a larger number of oxygen atoms per unit volume than the inner part of the first insulating film is formed on at least one of an interface between the first insulating film and the metal and an interface between the first insulating film and a second insulating film.

Claims

1. A method for manufacturing a semiconductor device including a multilayer wiring comprising:

a semiconductor substrate;

an insulating film formed on the semiconductor substrate such, at least one part of the insulating film being formed of a first insulating film;

a wiring groove and a via hole formed in the insulating film;

a wire and a connecting plug formed from a metal respectively filled in the wiring groove and the via hole; and

a modified layer formed on an interface between the first insulating film and the metal,

wherein the first insulating film is at least one layer insulating film including a siloxane structure containing silicon, oxygen and carbon,

the siloxane structure in the inner part of the first insulating film contains a larger number of carbon atoms than the number of silicon atoms, and

the modified layer contains a smaller number of carbon atoms and a larger number of oxygen atoms per unit volume than the inner part of the first insulating film, the method comprising;

forming the first insulating film containing the siloxane structure;

forming a hard mask film on the first insulating film;

applying a photoresist to the hard mask film and then patterning a groove thereon;

forming a mask pattern through forming a groove in the hard mask film by a dry etching using the photoresist as a mask;

removing the photoresist by an oxygen asking;

forming the wiring groove and the via hole in the first insulating film by a dry etching using the mask pattern as a mask;

forming the modified layer by performing modification treatment onto side faces of the wiring groove and the via hole in the first insulating film; and

forming the wire and the connecting plug respectively by filling the wiring groove and the via hole with the metal.

2. The method for manufacturing a semiconductor device according to claim 1,

wherein the modification treatment is an oxidation treatment.

3. The method for manufacturing a semiconductor device according to claim 2,

wherein the oxidation treatment is treatment with the use of oxygen plasma.

4. The method for manufacturing a semiconductor device according to claim 3,

wherein the oxygen plasma is a mixture gas of oxygen and Ar into a plasma state.

5. The method for manufacturing a semiconductor device according to claim 3,

wherein the oxygen plasma is formed by applying a substrate bias to a gas containing oxygen to convert the gas containing oxygen to a plasma state.

6. The method for manufacturing a semiconductor device according to claim 2,

wherein the oxidation treatment is carried out by using an ultraviolet ray and ozone.

7. The method for manufacturing a semiconductor device according to claim 2,

wherein the oxidation treatment is carried out by using an oxygen annealing operation.

8. The method for manufacturing a semiconductor device according to claim 1,

wherein the modification treatment is carried out by using nitrogen plasma.

9. The method for manufacturing a semiconductor device according to claim 1,

wherein in forming the wiring groove and the via hole, an etching gas used in the dry etching is a mixture gas containing at least Ar, N₂, O₂ and CF₄.

10. A method for manufacturing a semiconductor device including a multilayer wiring comprising:

a semiconductor substrate;

an insulating film formed on the semiconductor substrate, at least one part of the insulating film being formed of a first insulating film and a second insulating film;

a wiring groove and a via hole formed in the insulating film;

a wire and a connecting plug formed from a metal respectively filled in the wiring groove and the via hole; and

a modified layer formed on an interface between the first insulating film and the metal and an interface between the first insulating film and the second insulating film,

wherein the first insulating film is at least one layer insulating film including a siloxane structure containing silicon, oxygen and carbon,

the siloxane structure in the inner part of the first insulating film contains a larger number of carbon atoms than the number of silicon atoms, and

the modified layer contains a smaller number of carbon atoms and a larger number of oxygen atoms per unit volume than the inner part of the first insulating film, the method comprising;

forming the second insulating film containing a cyclic siloxane structure containing silicon, oxygen and carbon;

forming the modified layer by performing modification treatment onto a surface of the second insulating film;

forming the first insulating film on the modified layer;

forming a hard mask film on the first insulating film;

applying a photoresist to the hard mask film and then patterning a groove thereon;

forming a mask pattern through forming a groove in the hard mask film by a dry etching using the photoresist as a mask;

removing the photoresist by an oxygen ashing;

forming the wiring groove and the via hole in the first insulating film and the second insulating film by a dry etching using the mask pattern as a mask;

forming the modified layer by performing modification treatment onto side faces of the wiring groove and the via hole in the first insulating film and the second insulating film; and

forming the wire and the connecting plug respectively by filling the wiring groove and the via hole with the metal.

11. The method for manufacturing a semiconductor device according to claim 10,

wherein the modification treatment is an oxidation treatment.

12. The method for manufacturing a semiconductor device according to claim 11,

wherein the oxidation treatment is treatment with the use of oxygen plasma.

13. The method for manufacturing a semiconductor device according to claim 12,

wherein the oxygen plasma is a mixture gas of oxygen and Ar into a plasma state.

14. The method for manufacturing a semiconductor device according to claim 12,

wherein the oxygen plasma is formed by applying a substrate bias to a gas containing oxygen to convert the gas containing oxygen to a plasma state.

15. The method for manufacturing a semiconductor device according to claim 11,

wherein the oxidation treatment is carried out by using an ultraviolet ray and ozone.

16. The method for manufacturing a semiconductor device according to claim 11,

wherein the oxidation treatment is carried out by using an oxygen annealing operation.

17. The method for manufacturing a semiconductor device according to claim 10,

wherein the modification treatment is carried out by using nitrogen plasma.

18. The method for manufacturing a semiconductor device according to claim 10,

wherein in forming the wiring groove and the via hole, an etching gas used in the dry etching is a mixture gas containing at least Ar, N₂, O₂ and CF₄.