Capping before barrier-removal IC fabrication method

• US 8,043,958 B1
• Filed: 09/03/2010
• Issued: 10/25/2011
• Est. Priority Date: 10/13/2005
• Status: Expired due to Fees

• Current Assignee: Novellus Systems Incorporated (LAM Research Corporation)
• Original Assignee: Novellus Systems Incorporated (LAM Research Corporation)
• Inventors: Webb, Eric G., Stowell, R. Marshall, Minshall, Edmund B., Kepten, Avishai, Reid, Jonathan D., Mayer, Steven T.
• Primary Examiner(s): Coleman; William D
• Application Number:
  US12/875,857
• Time in Patent Office: 417 Days
• Field of Search: 438/622, 438/690, 438/678, 451/64, 156/345.12, 213/2
• US Class Current: 438/622
• CPC Class Codes: C23C 18/1607 by direct patterning
• CPC Class Codes: C23C 18/1882 Use of organic or inorganic compounds other than metals, e.g. activation, sensitisation with polymers
• CPC Class Codes: C25D 5/02 Electroplating of selected surface areas
• CPC Class Codes: C25D 7/123 Semiconductors first coated with a seed layer or a conductive layer
• CPC Class Codes: H01L 21/02074 the processing being a planarization of conductive layers
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: Y10S 414/135 Associated with semiconductor wafer handling

Abstract

Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.

Claims

1. A method of processing a semiconductor substrate, the method comprising:

(a) providing a semiconductor substrate comprising a dielectric layer having (i) copper lines disposed therein, (ii) a barrier layer on at least field regions of the dielectric layer, and (iii) copper overburden covering the copper lines and the barrier layer;

(b) removing the copper overburden by a technique other than an isotropic wet etch to expose the barrier layer;

(c) isotropically wet etching copper from said copper lines to form recesses in the copper lines by contacting the semiconductor substrate with an isotropic wet etchant comprising a complexing agent and an oxidizer and having a pH of greater than 5.

2. The method of claim 1, further comprising:

(d) depositing a capping layer material on at least the recessed copper lines of the semiconductor substrate.

3. The method of claim 1, wherein (b) comprises removing copper overburden by chemical mechanical polishing.

4. The method of claim 1, wherein (b) comprises removing copper overburden by an abrasive-free planarization.

5. The method of claim 1, wherein isotropically etching copper comprises selectively removing copper in the presence of exposed diffusion barrier.

6. The method of claim 1, wherein the barrier layer comprises at least one of tantalum, titanium, and tungsten.

7. The method of claim 2, wherein depositing the capping layer material comprises an electroless process.

8. The method of claim 2, wherein the capping layer material comprises cobalt or an alloy thereof.

9. The method of claim 2, further comprising thinning the semiconductor substrate after (d) to remove some fraction of the capping layer material deposited in (d), while maintaining at least some of the capping layer material over the exposed copper lines.

10. The method of claim 2, wherein depositing a capping layer material forms a layer of said capping material selectively over the exposed conductive lines without depositing the capping layer on the barrier.

11. The method of claim 2, wherein depositing the capping layer material comprises an electrolytic process.

12. The method of claim 10, wherein depositing a capping layer material comprises electroless plating.

13. The method of claim 10, wherein depositing a capping layer material comprises electroplating.