Microdisplay packaging system
First Claim
Patent Images
1. A method comprising:
- fabricating at least one set of imaging elements on an upper surface of a semiconductor substrate; and
affixing a base to a lower surface of the semiconductor substrate to generate substantially negligible mechanical stress between the semiconductor substrate and the base in a case that the imaging elements are operated within a range of operating temperatures;
wherein the at least one set of imaging elements comprises a pixel cell array and a liquid crystal layer; and
wherein affixing the base comprises;
applying an epoxy to one or both of the base and the lower surface of the semiconductor substrate;
bringing the base and the lower surface into contact with one another while at a temperature equal to at least one operating temperature of the imaging elements; and
partially curing the epoxy at least one operating temperature of the imaging elements.
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Abstract
Some embodiments provide a microdisplay integrated circuit (IC), a substantially transparent protective cover coupled to the microdisplay IC, and a base coupled to the microdisplay IC. Thermal expansion characteristics of the base may be substantially similar to thermal expansion characteristics of the protective cover. According to some embodiments, at least one set of imaging elements is fabricated on an upper surface of a semiconductor substrate, and a base is affixed to a lower surface of the semiconductor substrate to generate substantially negligible mechanical stress between the semiconductor substrate and the base.
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Citations
25 Claims
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1. A method comprising:
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fabricating at least one set of imaging elements on an upper surface of a semiconductor substrate; and affixing a base to a lower surface of the semiconductor substrate to generate substantially negligible mechanical stress between the semiconductor substrate and the base in a case that the imaging elements are operated within a range of operating temperatures; wherein the at least one set of imaging elements comprises a pixel cell array and a liquid crystal layer; and wherein affixing the base comprises; applying an epoxy to one or both of the base and the lower surface of the semiconductor substrate; bringing the base and the lower surface into contact with one another while at a temperature equal to at least one operating temperature of the imaging elements; and partially curing the epoxy at least one operating temperature of the imaging elements. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method comprising:
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fabricating at least one set of imaging elements on an upper surface of a semiconductor substrate; and affixing a base to a lower surface of the semiconductor substrate to substantially flatten the semiconductor substrate; wherein the at least one set of imaging elements comprises a pixel cell array and a liquid crystal layer; and wherein affixing the base comprises; applying an epoxy to one or both of the base and the lower surface of the semiconductor substrate; bringing the base and the lower surface into contact with one another while at a temperature equal to at least one operating temperature of the imaging elements; and partially curing the epoxy at least one operating temperature of the imaging elements. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A method comprising:
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fabricating at least one set of imaging elements on an upper surface of a semiconductor substrate, wherein the at least one set of imaging elements comprises a pixel cell array and a liquid crystal layer; affixing a base to a lower surface of the semiconductor substrate to generate substantially negligible mechanical stress between the semiconductor substrate and the base in a case that the imaging elements are operated within a range of operating temperatures; coupling a protective cover to the liquid crystal layer; and coupling a chip carrier to the base, the chip carrier defining a recess, the base mounted within the recess; wherein the pixel cell array is integrated with the semiconductor substrate and wherein the liquid crystal layer is in contact with the pixel cell array; wherein thermal expansion characteristics of the base are substantially similar to thermal expansion characteristics of the protective cover; and wherein a foot bounds a bottom of the recess, the foot having a first thickness that is substantially smaller than a thickness of the semiconductor substrate, the pixel cell array, the liquid crystal layer, the cover and the base.
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24. A method comprising:
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fabricating at least one set of imaging elements on an upper surface of a semiconductor substrate; and affixing a base to a lower surface of the semiconductor substrate to generate substantially negligible mechanical stress between the semiconductor substrate and the base in a case that the imaging elements are operated within a range of operating temperatures; wherein the at least one set of imaging elements comprises a pixel cell array and a liquid crystal layer; and wherein the thermal expansion characteristics of the base are different than thermal expansion characteristics of the semiconductor substrate such that an interface of the base and the semiconductor substrate would be subjected to significant mechanical stresses in a case that the imaging elements are operated within a range of operating temperatures without said affixing of the base to the lower surface of the semiconductor substrate to generate substantially negligible mechanical stress between the semiconductor substrate and the base in the case that the imaging elements are operated within a range of operating temperatures.
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25. A method comprising:
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fabricating at least one set of imaging elements on an upper surface of a semiconductor substrate; and affixing a base to a lower surface of the semiconductor substrate to substantially flatten the semiconductor substrate; wherein the at least one set of imaging elements comprises a pixel cell array and a liquid crystal layer; wherein affixing the base comprises;
affixing the base to the lower surface of the semiconductor substrate to substantially flatten the semiconductor substrate in a case that the imaging elements are operated within a range of operating temperatures; andwherein the thermal expansion characteristics of the base are different than thermal expansion characteristics of the semiconductor substrate such that an interface of the base and the semiconductor substrate would be subjected to significant mechanical stresses in a case that the imaging elements are operated within a range of operating temperatures without said affixing the base to the lower surface of the semiconductor substrate to substantially flatten the semiconductor substrate in a case that the imaging elements are operated within a range of operating temperatures.
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Specification