Microdisplay packaging system

• US 8,044,431 B2
• Filed: 06/03/2008
• Issued: 10/25/2011
• Est. Priority Date: 12/31/2003
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: O'Connor, Michael, Ward-Dolkas, Paul C., Springett, Thomas W.
• Primary Examiner(s): MITCHELL, JAMES M
• Application Number:
  US12/132,183
• Publication Number:
  US 20080233667A1
• Time in Patent Office: 1,239 Days
• Field of Search: 257/59, 257/178, 257/440
• US Class Current: 257/178
• CPC Class Codes: G02F 1/1333 Constructional arrangements; Manufacturing methodsG02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/133308 Support structures for LCD panels, e.g. frames or bezels
• CPC Class Codes: G02F 1/136277 formed on a semiconductor substrate, e.g. of silicon
• CPC Class Codes: G02F 2201/54 Arrangements for reducing warping-twist
• CPC Class Codes: G02F 2203/60 Temperature independent

Abstract

Some embodiments provide a microdisplay integrated circuit (IC), a substantially transparent protective cover coupled to the microdisplay IC, and a base coupled to the microdisplay IC. Thermal expansion characteristics of the base may be substantially similar to thermal expansion characteristics of the protective cover. According to some embodiments, at least one set of imaging elements is fabricated on an upper surface of a semiconductor substrate, and a base is affixed to a lower surface of the semiconductor substrate to generate substantially negligible mechanical stress between the semiconductor substrate and the base.

Claims

1. A method comprising:

fabricating at least one set of imaging elements on an upper surface of a semiconductor substrate; and

affixing a base to a lower surface of the semiconductor substrate to generate substantially negligible mechanical stress between the semiconductor substrate and the base in a case that the imaging elements are operated within a range of operating temperatures;

wherein the at least one set of imaging elements comprises a pixel cell array and a liquid crystal layer; and

wherein affixing the base comprises;

applying an epoxy to one or both of the base and the lower surface of the semiconductor substrate;

bringing the base and the lower surface into contact with one another while at a temperature equal to at least one operating temperature of the imaging elements; and

partially curing the epoxy at least one operating temperature of the imaging elements.

2. A method according to claim 1, wherein thermal expansion characteristics of the base are substantially similar to thermal expansion characteristics of a protective cover, and wherein the imaging elements are disposed between the cover and the semiconductor substrate.

3. A method according to claim 1, wherein the pixel cell array is integrated with the semiconductor substrate and wherein the liquid crystal layer is in contact with the pixel cell array.

4. A method according to claim 3, further comprising:

coupling a protective cover to the liquid crystal layer;

wherein thermal expansion characteristics of the base are substantially similar to thermal expansion characteristics of the protective cover.

5. A method according to claim 4, further comprising:

coupling a chip carrier to the base, the chip carrier defining a recess, the base mounted within the recess.

6. A method according to claim 5, wherein the chip carrier defines an opening and wherein the protective cover extends partially into, fully into, partially through or fully through the opening.

7. A method according to claim 5, wherein the chip carrier defines an opening and wherein the base extends partially into, fully into, partially through or fully through the opening.

8. A method according to claim 7, further comprising:

coupling a heat sink to the base.

9. A method according to claim 5, further comprising:

coupling a heat sink to the chip carrier.

10. A method according to claim 1, wherein the thermal expansion characteristics of the base are different than thermal expansion characteristics of the semiconductor substrate such that an interface of the base and the semiconductor substrate would be subjected to significant mechanical stresses in a case that the imaging elements are operated within a range of operating temperatures without said affixing of the base to the lower surface of the semiconductor substrate to generate substantially negligible mechanical stress between the semiconductor substrate and the base in the case that the imaging elements are operated within a range of operating temperatures.

11. A method comprising:

fabricating at least one set of imaging elements on an upper surface of a semiconductor substrate; and

affixing a base to a lower surface of the semiconductor substrate to substantially flatten the semiconductor substrate;

wherein the at least one set of imaging elements comprises a pixel cell array and a liquid crystal layer; and

wherein affixing the base comprises;

applying an epoxy to one or both of the base and the lower surface of the semiconductor substrate;

bringing the base and the lower surface into contact with one another while at a temperature equal to at least one operating temperature of the imaging elements; and

partially curing the epoxy at least one operating temperature of the imaging elements.

12. A method according to claim 11, wherein affixing the base comprises:

affixing the base to the lower surface of the semiconductor substrate to substantially flatten the semiconductor substrate in a case that the imaging elements are operated within a range of operating temperatures.

13. A method according to claim 12, wherein the thermal expansion characteristics of the base are different than thermal expansion characteristics of the semiconductor substrate such that an interface of the base and the semiconductor substrate would be subjected to significant mechanical stresses in a case that the imaging elements are operated within a range of operating temperatures without said affixing the base to the lower surface of the semiconductor substrate to substantially flatten the semiconductor substrate in a case that the imaging elements are operated within a range of operating temperatures.

14. A method according to claim 11, wherein the thermal expansion characteristics of the base are different than thermal expansion characteristics of the semiconductor substrate such that an interface of the base and the semiconductor substrate would be subjected to significant mechanical stresses in a case that the imaging elements are operated within a range of operating temperatures without said affixing the base to the lower surface of the semiconductor substrate to substantially flatten the semiconductor substrate in a case that the imaging elements are operated within a range of operating temperatures.

15. A method according to claim 11, wherein the pixel cell array is integrated with the semiconductor substrate and wherein the liquid crystal layer is in contact with the pixel cell array.

16. A method according to claim 15, further comprising:

coupling a protective cover to the liquid crystal layer;

wherein thermal expansion characteristics of the base are substantially similar to thermal expansion characteristics of the protective cover.

17. A method according to claim 16, further comprising:

coupling a chip carrier to the base, the chip carrier defining a recess, the base mounted within the recess.

18. A method according to claim 17, wherein a foot bounds a bottom of the recess, the foot having a first thickness that is substantially smaller than a thickness of the semiconductor substrate, the pixel cell array, the liquid crystal layer, the cover and the base.

19. A method according to claim 17, wherein the chip carrier defines an opening and wherein the protective cover extends partially into, fully into, partially through or fully through the opening.

20. A method according to claim 17, wherein the chip carrier defines an opening and wherein the base extends partially into, fully into, partially through or fully through the opening.

21. A method according to claim 20, further comprising:

coupling a heat sink to the base.

22. A method according to claim 17, further comprising:

coupling a heat sink to the chip carrier.

23. A method comprising:

fabricating at least one set of imaging elements on an upper surface of a semiconductor substrate, wherein the at least one set of imaging elements comprises a pixel cell array and a liquid crystal layer;

affixing a base to a lower surface of the semiconductor substrate to generate substantially negligible mechanical stress between the semiconductor substrate and the base in a case that the imaging elements are operated within a range of operating temperatures;

coupling a protective cover to the liquid crystal layer; and

coupling a chip carrier to the base, the chip carrier defining a recess, the base mounted within the recess;

wherein the pixel cell array is integrated with the semiconductor substrate and wherein the liquid crystal layer is in contact with the pixel cell array;

wherein thermal expansion characteristics of the base are substantially similar to thermal expansion characteristics of the protective cover; and

wherein a foot bounds a bottom of the recess, the foot having a first thickness that is substantially smaller than a thickness of the semiconductor substrate, the pixel cell array, the liquid crystal layer, the cover and the base.

24. A method comprising:

fabricating at least one set of imaging elements on an upper surface of a semiconductor substrate; and

affixing a base to a lower surface of the semiconductor substrate to generate substantially negligible mechanical stress between the semiconductor substrate and the base in a case that the imaging elements are operated within a range of operating temperatures;

wherein the at least one set of imaging elements comprises a pixel cell array and a liquid crystal layer; and

wherein the thermal expansion characteristics of the base are different than thermal expansion characteristics of the semiconductor substrate such that an interface of the base and the semiconductor substrate would be subjected to significant mechanical stresses in a case that the imaging elements are operated within a range of operating temperatures without said affixing of the base to the lower surface of the semiconductor substrate to generate substantially negligible mechanical stress between the semiconductor substrate and the base in the case that the imaging elements are operated within a range of operating temperatures.

25. A method comprising:

fabricating at least one set of imaging elements on an upper surface of a semiconductor substrate; and

affixing a base to a lower surface of the semiconductor substrate to substantially flatten the semiconductor substrate;

wherein the at least one set of imaging elements comprises a pixel cell array and a liquid crystal layer;

wherein affixing the base comprises;

affixing the base to the lower surface of the semiconductor substrate to substantially flatten the semiconductor substrate in a case that the imaging elements are operated within a range of operating temperatures; and

wherein the thermal expansion characteristics of the base are different than thermal expansion characteristics of the semiconductor substrate such that an interface of the base and the semiconductor substrate would be subjected to significant mechanical stresses in a case that the imaging elements are operated within a range of operating temperatures without said affixing the base to the lower surface of the semiconductor substrate to substantially flatten the semiconductor substrate in a case that the imaging elements are operated within a range of operating temperatures.