Nonvolatile semiconductor memory device

• US 8,044,448 B2
• Filed: 07/24/2009
• Issued: 10/25/2011
• Est. Priority Date: 07/25/2008
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kamigaichi, Takeshi, Arai, Fumitaka
• Primary Examiner(s): Tran; Tan N
• Application Number:
  US12/508,904
• Publication Number:
  US 20100020608A1
• Time in Patent Office: 823 Days
• Field of Search: 257/296, 257/390, 365/185.05, 365/184
• US Class Current: 257/296
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A nonvolatile semiconductor memory device includes: a memory cell array region having memory cells connected in series; a control circuit region disposed below the memory cell array region; and an interconnection portion electrically connecting the control circuit region and the memory cell array region. The memory cell array region includes: a plurality of first memory cell regions having the memory cells; and a plurality of connection regions. The interconnection portion is provided in the connection regions. The first memory cell regions are provided at a first pitch in a first direction orthogonal to a lamination direction of the memory cell array region and the control circuit region. The connection regions are provided between the first memory cell regions mutually adjacent in the first direction, and at a second pitch in a second direction orthogonal to the lamination direction and the first direction.

Claims

1. A nonvolatile semiconductor memory device comprising:

a memory cell array region having memory cells connected in series;

a control circuit region disposed below the memory cell array region; and

an interconnection portion electrically connecting the control circuit region and the memory cell array region,

the memory cell array region including;

a plurality of first memory cell regions having the memory cells; and

a plurality of connection regions, the interconnection portion being provided in the connection regions,

the first memory cell regions being provided at a first pitch in a first direction orthogonal to a lamination direction of the memory cell array region and the control circuit region; and

the connection regions being provided between the first memory cell regions mutually adjacent in the first direction, and at a second pitch in a second direction orthogonal to the lamination direction and the first direction.

2. The device according to claim 1, wherein

the memory cell array region further includes a plurality of second memory cell regions provided between the first memory cell regions adjacent in the first direction and having the memory cell, and

the second memory cell regions are provided at a third pitch in the second direction.

3. The device according to claim 2, wherein

the memory cell array region further includes:

a plurality of first conductive layers laminated in the lamination direction to extend in the first direction;

a semiconductor layer provided facing a side wall of each of the first conductive layers in the first memory cell region; and

a charge storage layer provided between each of the first conductive layers and the semiconductor layer in the first memory cell region,

the first conductive layers further includes a stairstep portion formed in a stairstep configuration in the connection region,

the first conductive layer in the first memory cell region and the connection region is formed in a straight-line configuration along the first direction,

the first conductive layer between the first memory cell regions mutually adjacent in the first direction is formed to curve to the second direction side to avoid the connection region, and

the interconnection portion connects the stairstep portion and a conductive layer of the control circuit region,

the semiconductor layer has a U-shape,

the memory cell array region further includes;

a second conductive layer, a third conductive layer and a fourth conductive layer,

the second conductive layer is electrically connected to one end of the semiconductor layer and extends in the first direction in a layer above the first conductive layers in the first memory cell region,

the third conductive layer is electrically connected to the second conductive layer and extends in the first direction in a layer above the second conductive layer in a region between the first memory cell regions mutually adjacent in the first direction, a position of the third conductive layer in the second direction matching a position of the second conductive layer in the second direction, and

the fourth conductive layer is electrically connected to another end of the semiconductor layer and extends in the second direction in the first memory cell region,

the third conductive layer is formed in a layer above the fourth conductive layer, and

the fourth conductive layer is further provided in the second memory cell region.

4. The device according to claim 1, wherein the memory cell array region further includes

a plurality of first conductive layers laminated in the lamination direction to extend in the first direction, and

a plurality of semiconductor layers passing through the first conductive layers in the lamination direction in the first memory cell region,

two mutually adjacent semiconductor layers of the semiconductor layers are electrically connected in a lower side of the memory cell array layer.

5. The device according to claim 1, wherein the memory cell array region further includes:

a plurality of first conductive layers laminated in the lamination direction to extend in the first direction, and

a plurality of semiconductor layers passing through the first conductive layers in the lamination direction in the first memory cell region,

a distance in the first direction between a lower conductive layer of the first conductive layers and a center of the connection region in the first direction is smaller than a distance in the first direction between the center of the connection region in the first direction and an upper conductive layer above the lower conductive layer of the first conductive layers.

6. The device according to claim 1, wherein

the memory cell array region further includes:

a plurality of first conductive layers laminated in the lamination direction to extend in the first direction;

a semiconductor layer provided facing a side wall of each of the first conductive layers in the first memory cell region; and

a charge storage layer provided between each of the first conductive layers and the semiconductor layer in the first memory cell region,

the first conductive layers further includes a stairstep portion formed in a stairstep configuration in the connection region,

the first conductive layer in the first memory cell region and the connection region is formed in a straight-line configuration along the first direction,

the first conductive layer between the first memory cell regions mutually adjacent in the first direction is formed to curve to the second direction side to avoid the connection region, and

the interconnection portion connects the stairstep portion and a conductive layer of the control circuit region.

7. The device according to claim 6, wherein

the semiconductor layer has a U-shape,

the memory cell array region further includes:

a second conductive layer, a third conductive layer and a fourth conductive layer,

the second conductive layer is electrically connected to one end of the semiconductor layer and extends in the first direction in a layer above the first conductive layers in the first memory cell region,

the third conductive layer is electrically connected to the second conductive layer and extends in the first direction in a layer above the second conductive layer in a region between the first memory cell regions mutually adjacent in the first direction, a position of the third conductive layer in the second direction matching a position of the second conductive layer in the second direction, and

the fourth conductive layer is electrically connected to another end of the semiconductor layer and extends in the second direction in the first memory cell region.