Semiconductor device with trench field plate including first and second semiconductor materials

• US 8,044,459 B2
• Filed: 11/10/2008
• Issued: 10/25/2011
• Est. Priority Date: 11/10/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Roesch, Maximilian, Wood, Andrew, Poelzl, Martin, Born, Mathias, Ropohl, Jan, Blank, Oliver, Hirler, Franz, Hiller, Uli, Siemieniec, Ralf, Rieger, Walter, Haeberlen, Oliver, Zelsacher, Rudolf, Krumrey, Joachim
• Primary Examiner(s): Dang; Phuc T
• Application Number:
  US12/268,182
• Publication Number:
  US 20100117144A1
• Time in Patent Office: 1,079 Days
• Field of Search: 257/330
• US Class Current: 257/330
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In one embodiment, a field effect transistor has a semiconductor body, a drift region of a first conductivity type and a gate electrode. At least one trench extends into the drift region. A field plate is arranged at least in a portion of the at least one trench. A dielectric material at least partially surrounds both the gate electrode and the field plate. The field plate includes a first semiconducting material.

Claims

1. A semiconductor device comprising:

a semiconductor body;

a drift region of a first conductivity type;

at least one trench extending into the drift region;

at least one gate electrode;

a field plate in at least a portion of the at least one trench; and

a dielectric material, wherein the dielectric material at least partially surrounds the gate electrode and the field plate;

wherein the field plate comprises a first semiconducting material at least partially of a second conductivity type and a second semiconducting material of the first conductivity type, the second conductivity type being complementary to the first conductivity type, and a diffusion barrier layer arranged at least partially between the first semiconducting material and the second semiconducting material.

2. The semiconductor device of claim 1, wherein the at least one gate electrode is arranged in an upper portion of the at least one trench and the field plate is at least partially arranged in a lower portion of the at least one trench.

3. The semiconductor device of claim 1, wherein the number of charge carriers of the first conductivity type in the drift region is essentially equal to the number of charge carriers of the second conductivity type in the first semiconducting material.

4. The semiconductor device of claim 1, wherein the field plate comprises a contact region, the contact region electrically coupling the field plate to a first electrode.

5. The semiconductor device of claim 4, wherein the contact region comprises one of a group comprising highly doped polysilicon, a silicide and a metal.

6. The semiconductor device of claim 1, wherein the first semiconducting material comprises a doping concentration N with N≦

5·

10¹⁷ cm<sup>−

3</sup>.

7. The semiconductor device of claim 1, wherein the first semiconducting material comprises a doping concentration N with N≦

2·

10¹⁶ cm<sup>−

3</sup>.

8. The semiconductor device of claim 1, wherein the first semiconducting material comprises one of group comprising a constant doping concentration, a nitrided semiconducting material, and a lightly doped polysilicon.

9. The semiconductor device of claim 1, wherein the first semiconducting material comprises a variable doping concentration, the variable doping concentration decreasing in a vertical direction towards a base of the at least one trench.

10. The semiconductor device of claim 1, wherein the first semiconducting material comprises a graded doping concentration, the graded doping concentration decreasing in a vertical direction towards a base of the at least one trench.

11. The semiconductor device of claim 1, wherein the first semiconducting material comprises a stepped graded doping concentration, the stepped graded doping concentration decreasing in a vertical direction towards a base of the at least one trench.

12. The semiconductor device of claim 1, wherein the first semiconducting material comprises a Gaussian doping concentration in a vertical direction towards a base of the at least one trench.

13. The semiconductor device of claim 1 configured as a field effect transistor.

14. The semiconductor device of claim 1, wherein the field plate comprises centers of recombination.

15. The semiconductor device of claim 1, wherein the field plate further comprises a metal.

16. The semiconductor device of claim 15, wherein the metal is selected from the group consisting of gold and platinum.

17. The semiconductor device of claim 15, wherein a further layer is arranged at least partially between the metal and the first semiconducting material.

18. A semiconductor device comprising:

a semiconductor body;

a drift region of a first conductivity type;

at least one trench extending into the drift region;

at least one gate electrode;

a field plate in at least a portion of the at least one trench, the field plate comprising a first semiconducting material that is at least partially of a second conductivity type, the second conductivity type that is complementary to the first conductivity type; and

a dielectric material at least partially surrounding the gate electrode and the field plate;

wherein the field plate further comprises a second semiconducting material of the first conductivity type, the second semiconducting material being arranged at least partially between the first semiconducting material and a contact region and adjacent to the contact region and comprising a doping concentration higher than a doping concentration of the first semiconducting material, and a diffusion barrier layer, the diffusion barrier layer being arranged at least partially between the first semiconducting material and the second semiconducting material.

19. The semiconductor device of claim 18, wherein the second semiconducting material comprises highly doped polysilicon.

20. The semiconductor device of claim 18, wherein the diffusion barrier layer comprises a material selected from the group consisting of oxides and nitrides.

21. A field effect transistor comprising:

a semiconductor body;

a drift region of a first conductivity type;

at least one trench extending into the drift region;

at least one gate electrode;

a field plate in at least a portion of the at least one trench; and

a dielectric material, wherein the dielectric material at least partially surrounds the gate electrode and the field plate;

wherein the field plate comprises a first semiconducting material at least partially of a second conductivity type and a second semiconducting material of the first conductivity type, the second conductivity type being complementary to the first conductivity type, and a diffusion barrier layer arranged at least partially between the first semiconducting material and the second semiconducting material.

22. A method comprising:

providing a semiconductor body, a drift region of a first conductivity type, at least one trench extending into the drift region, at least one gate electrode, and a field plate comprising a first semiconducting material in at least a portion of the at least one trench;

depositing a dielectric material such that it at least partially surrounds the gate electrode and the field plate, wherein the field plate comprises the first semiconducting material at least partially of a second conductivity type and a second material of the first conductivity type, the second conductivity type being complementary to the first conductivity type; and

arranging a diffusion barrier layer at least partially between the first semiconducting material and the second semiconducting material.