Electronic device with connecting structure

• US 8,044,460 B2
• Filed: 11/29/2007
• Issued: 10/25/2011
• Est. Priority Date: 12/01/2006
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Hirler, Franz, Zundel, Markus
• Primary Examiner(s): Parker; Kenneth
• Assistant Examiner(s): Lin; John
• Application Number:
  US11/947,552
• Publication Number:
  US 20080128803A1
• Time in Patent Office: 1,426 Days
• Field of Search: 257328-332, 257/E29.027, 257/E29.118, 257/E29.121, 257/E29.122, 257/E29.131, 257/E29.257, 257/E29.262, 257202-211, 438/270
• US Class Current: 257/331
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/945 Trench capacitors

Abstract

A connecting structure for an electronic device includes an edge region of the device, a first trench and a second trench running toward the edge region, a first electrode within the first trench, and a second electrode within the second trench, the first and second electrodes being arranged in a same electrode plane with regard to a main surface of a substrate of the electronic device within the trenches, and the first electrode extending, at an edge region side end of the first trench, farther toward the edge region than the second electrode extends, at an edge region side end of the second trench, toward the edge region.

Claims

1. A semiconductor device including a connecting structure comprising:

a first edge region;

a second edge region opposite the first edge region;

a central region arranged between the first edge region and the second edge region;

first, second, and third trenches running toward the first edge region and the second edge region;

a first electrode within the first trench, a second electrode within the second trench, and a third electrode within the third trench,

the first, second, and third electrodes being arranged in an electrode plane arranged with regard to a main surface of a substrate of the electronic device;

the first electrode extending farther into the first edge region than the second electrode and the third electrode;

the third electrode extending farther into the second edge region than the first electrode and the second electrode;

the first and third electrodes not extending into the central region;

the first electrode and the third electrode being arranged on a straight connecting line;

the second electrode being arranged offset to the connecting line; and

the first electrode and the third electrode being contacted with a connection structure for a first potential, and the second electrode being connected with a connection structure for a second potential,

wherein the second trench extends through the central region, wherein a first portion of the second trench and a portion of the first trench are arranged side by side in a lateral direction with respect to the main surface of the substrate and wherein a second portion of the second trench and a portion of the third trench are arranged side by side in the lateral direction with respect to the main surface of the substrate.

2. The semiconductor device of claim 1, wherein the connection structure for the first potential contacts the first electrode within the first edge region and the third electrode within the second edge region.

3. The semiconductor device of claim 1, wherein the connection structure for the first potential and/or the connection structure for the second potential comprise(s) a contacting area.

4. The semiconductor device of claim 1, wherein the first trench further comprises a first lower electrode arranged below the first electrode in relation to the main surface of the substrate, and wherein the third trench further comprises a third lower electrode arranged below the third electrode in relation to the main surface of the substrate, the first lower electrode and the third lower electrode being arranged on a second electrode plane within the first trench and the third trench, respectively.

5. The semiconductor device of claim 4, wherein the first lower electrode and the third lower electrode are connected to the connection structure for the second potential.

6. The semiconductor device of claim 1, wherein the second trench further comprises a second lower electrode arranged below the second electrode in relation to the main surface of the substrate, the second electrode and the second lower electrode being arranged on two electrode planes within the second trench.

7. The semiconductor device of claim 1 further comprising a plurality of first trenches having first electrodes associated respectively, and a plurality of third trenches having third electrodes associated respectively, and/or a plurality of second trenches having second electrodes associated respectively.

8. The semiconductor device of claim 7, wherein a second trench is arranged adjacent to both sides of first and third trenches, and/or first and third trenches, respectively, are arranged adjacent to both sides of a second trench.

9. The semiconductor device of claim 1, wherein at least one insulation layer is arranged between the first electrode and the substrate, the second electrode and the substrate and the third electrode and the substrate.

10. The semiconductor device of claim 1, wherein the first and third electrodes are gate electrodes and wherein the second electrode is a source electrode.

11. The semiconductor device of claim 1 comprising a plurality of second trenches and second electrodes, wherein central portions of the second electrodes are connected to a common metal structure.