Method of manufacturing a trench transistor having a heavy body region

• US 8,044,463 B2
• Filed: 04/07/2010
• Issued: 10/25/2011
• Est. Priority Date: 11/14/1997
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Mo, Brian S., Chau, Duc, Sapp, Steven, Bencuya, Izak, Probst, Dean E.
• Primary Examiner(s): Ha, Nathan
• Application Number:
  US12/755,966
• Publication Number:
  US 20100264487A1
• Time in Patent Office: 566 Days
• Field of Search: 257/341, 257/330, 257/E29.262
• US Class Current: 257/341
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

Claims

1. A trenched field effect transistor comprising:

a semiconductor substrate;

a trench extending a predetermined depth into said semiconductor substrate;

a pair of doped source junctions, positioned on opposite sides of the trench;

a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of said heavy body extending less deeply into said semiconductor substrate than said predetermined depth of said trench, and

a doped well surrounding the heavy body beneath the heavy body

wherein the depth of the doped heavy body region relative to the depth of the doped well is selected so that a peak electric field, when voltage is applied to the transistor, is spaced away from the trench.

2. The trenched field effect transistor of claim 1 wherein said doped well has a substantially flat bottom.

3. The trenched field effect transistor of claim 1 wherein said doped well has a depth less than the predetermined depth of said trench.

4. The trenched field effect transistor of claim 1 wherein said trench has rounded top and bottom corners.

5. The field effect transistor of claim 1 wherein the heavy body region forms an abrupt junction.

6. The field effect transistor of claim 5 wherein the heavy body comprises a heavily doped region formed by implanting dopants at location approximately that of the abrupt junction.

7. The field effect transistor of claim 1 wherein the trench is lined with a dielectric material and substantially filled with conductive material, wherein the conductive material substantially filling the trench is recessed relative to the surface of the substrate.

8. The field effect transistor of claim 1 wherein the substrate comprises a first highly doped region and a second doped region disposed above the first highly doped region, the second doped region having a lower doping concentration relative to the first highly doped region.

9. The field effect transistor of claim 8 further comprising a termination structure surrounding the transistor.

10. The field effect transistor of claim 9 wherein the termination structure comprises a doped region having dopants extending into the second doped region of the substrate to form a PN junction between the termination doped region and the second doped region of the substrate.

11. The field effect transistor of claim 9 wherein the termination structure comprises a trench.

12. The field effect transistor of claim 11 wherein the termination trench has a depth that is substantially the same as the depth of the transistor trench.

13. The field effect transistor of claim 9 wherein the termination structure comprises a plurality of concentric trenches surrounding the transistor.

14. The field effect transistor of claim 1 wherein a distance between a bottom of the doped heavy body to the doped well junction is less than approximately 0.5 μ

m.

15. A field effect transistor comprising:

a semiconductor substrate;

a gate trench extending a predetermined depth into the semiconductor substrate;

a doped source region that forms a source junction inside a doped well;

a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into the semiconductor substrate than the predetermined depth of the trench;

wherein the doped well surrounds the heavy body beneath the heavy body; and

wherein the depth of the doped heavy body region relative to the depth of the doped well is selected so that a peak electric field, when voltage is applied to the transistor, is spaced away from the trench.

16. The field effect transistor of claim 15 wherein the heavy body region forms an abrupt junction at the interface between the doped heavy body region and the doped well, such that, when voltage is applied to the transistor, a peak electric filed occurs near the area of the interface.

17. The field effect transistor of claim 15, wherein the doped well has a substantially flat bottom.

18. The field effect transistor of claim 15 wherein the doped well has a depth less than the predetermined depth of the gate trench.

19. The field effect transistor of claim 15 wherein the gate trench has rounded top corners.

20. The field effect transistor of claim 15 wherein a distance between a bottom of the doped heavy body to the doped well junction is less than approximately 0.5 μ

m.