Chip package
First Claim
Patent Images
1. A chip package comprising:
- a semiconductor chip comprising a CMOS device, a passivation layer over said CMOS device, wherein said passivation layer comprises a nitride layer, a metal pad having a contact point at a bottom of an opening in said passivation layer, wherein said opening is over said contact point, an optical filter over said passivation layer and said CMOS device, and a microlens over said optical filter, said passivation layer and said CMOS device;
a metal bump on said semiconductor chip, wherein said metal bump is connected to said contact point through said opening, wherein said metal bump comprises a titanium-containing layer, a gold seed layer on said titanium-containing layer and an electroplated gold layer having a thickness between 1 and 50 micrometers on said gold seed layer;
a transparent substrate over said semiconductor chip, wherein a cell is between said semiconductor chip and said transparent substrate and vertically over a photo-sensitive area of said semiconductor chip; and
a spacer between said semiconductor chip and said transparent substrate, wherein said spacer has a bottom end joining said semiconductor chip and a top end joining said transparent substrate, wherein said spacer is horizontally between said microlens and said metal bump.
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Accused Products
Abstract
A chip package includes a bump connecting said semiconductor chip and said circuitry component, wherein the semiconductor chip has a photosensitive area used to sense light. The chip package may include a ring-shaped protrusion connecting a transparent substrate and the semiconductor chip.
60 Citations
53 Claims
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1. A chip package comprising:
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a semiconductor chip comprising a CMOS device, a passivation layer over said CMOS device, wherein said passivation layer comprises a nitride layer, a metal pad having a contact point at a bottom of an opening in said passivation layer, wherein said opening is over said contact point, an optical filter over said passivation layer and said CMOS device, and a microlens over said optical filter, said passivation layer and said CMOS device; a metal bump on said semiconductor chip, wherein said metal bump is connected to said contact point through said opening, wherein said metal bump comprises a titanium-containing layer, a gold seed layer on said titanium-containing layer and an electroplated gold layer having a thickness between 1 and 50 micrometers on said gold seed layer; a transparent substrate over said semiconductor chip, wherein a cell is between said semiconductor chip and said transparent substrate and vertically over a photo-sensitive area of said semiconductor chip; and a spacer between said semiconductor chip and said transparent substrate, wherein said spacer has a bottom end joining said semiconductor chip and a top end joining said transparent substrate, wherein said spacer is horizontally between said microlens and said metal bump. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 42, 43, 44)
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9. A chip package comprising:
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a semiconductor chip comprising a CMOS device, a passivation layer over said CMOS device, wherein said passivation layer comprises a nitride layer, a metal pad having a contact point at a bottom of an opening in said passivation layer, wherein said opening is over said contact point, an optical filter over said passivation layer and said CMOS device, and a microlens over said optical filter, said passivation layer and said CMOS device; a metal bump on said semiconductor chip, wherein said metal bump is connected to said contact point through said opening, wherein said metal bump comprises an adhesion layer, a copper seed layer on said adhesion layer and an electroplated copper layer having a thickness between 1 and 100 micrometers on said copper seed layer; a transparent substrate over said semiconductor chip, wherein a cell is between said semiconductor chip and said transparent substrate and vertically over a photo-sensitive area of said semiconductor chip; and a spacer between said semiconductor chip and said transparent substrate, wherein said spacer has a bottom end joining said semiconductor chip and a top end joining said transparent substrate, wherein said spacer is horizontally between said microlens and said metal bump. - View Dependent Claims (10, 11, 12, 13, 14, 15, 45, 46, 47)
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16. A chip package comprising:
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a semiconductor chip comprising a CMOS device, a passivation layer over said CMOS device, wherein said passivation layer comprises a nitride layer, a metal pad having a contact point at a bottom of an opening in said passivation layer, wherein said opening is over said contact point, an optical filter over said passivation layer and said CMOS device, and a microlens over said optical filter, said passivation layer and said CMOS device; a metal bump on said semiconductor chip, wherein said metal bump is connected to said contact point through said opening, wherein said metal bump comprises a copper layer, a nickel-containing layer on said copper layer and a tin-containing layer having a thickness between 1 and 300 micrometers on said nickel-containing layer; a transparent substrate over said semiconductor chip, wherein a cell is between said semiconductor chip and said transparent substrate and vertically over a photo-sensitive area of said semiconductor chip; and a spacer between said semiconductor chip and said transparent substrate, wherein said spacer has a bottom end joining said semiconductor chip and a top end joining said transparent substrate, wherein said spacer is horizontally between said microlens and said metal bump. - View Dependent Claims (17, 18, 19, 20, 48, 49, 50)
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21. A chip package comprising:
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a semiconductor chip comprising multiple CMOS devices, an insulating layer over said multiple CMOS devices, wherein said insulating layer comprises an oxide layer, an optical filter over said insulating layer and said multiple CMOS devices, and multiple microlenses over said optical filter, said insulating layer and said multiple CMOS devices; a transparent substrate over said semiconductor chip, said multiple microlenses and said optical filter; a spacer between said semiconductor chip and said transparent substrate, wherein said spacer has a bottom end joining said semiconductor chip and a top end joining said transparent substrate, wherein a cell is between said semiconductor chip and said transparent substrate and vertically over a photo-sensitive area of said semiconductor chip; a metal interconnect connected to a metal pad of said semiconductor chip through an opening in said insulating layer, wherein said metal interconnect comprises a first adhesion layer, a copper-containing seed layer contacting said first adhesion layer, and a first electroplated copper layer having a thickness between 1 and 100 micrometers and contacting said copper-containing seed layer; a circuit component joining said semiconductor chip; and a tin-containing layer connected to said first electroplated copper layer, wherein said tin-containing layer is between said semiconductor chip and said circuit component, wherein said tin-containing layer has a thickness between 1 and 300 micrometers. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 51, 52, 53)
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29. A chip package comprising:
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a semiconductor chip comprising multiple CMOS devices, an insulating layer over said multiple CMOS devices, a metal pad having a contact point under a first opening in said insulating layer, an optical filter over said insulating layer and said multiple CMOS devices, and multiple microlenses over said optical filter, said insulating layer and said multiple CMOS devices; a transparent substrate over said semiconductor chip, said multiple microlenses and said optical filter, wherein said transparent substrate has a width less than that of said semiconductor chip; a spacer between said semiconductor chip and said transparent substrate, wherein said spacer has a bottom end joining said semiconductor chip and a top end joining said transparent substrate, wherein a cell is between said semiconductor chip and said transparent substrate and vertically over a photo-sensitive area of said semiconductor chip; a circuit component, wherein a second opening through said circuit component is vertically over said semiconductor chip; and a metal bump over said contact point, wherein said metal bump has a bottom end joining said contact point and a top end joining said circuit component. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41)
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Specification