Transistors, semiconductor devices, assemblies and constructions
First Claim
1. A semiconductor construction, comprising:
- a base;
an array of semiconductor material active areas supported by the base, the array comprising columns and rows of the active areas;
lines of first insulative material along the columns of the active areas, the lines directly contacting ends of the active areas;
the lines of first insulative material and rows of the active areas defining a lattice;
sections of second insulative material at locations between the rows and lines of the lattice, such that said sections alternate with active areas along the columns of the array; and
regions of the second insulative material under the active areas;
the regions extending from opposing sides of individual active areas to entirely separate the individual active areas from the base.
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Accused Products
Abstract
Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.
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Citations
9 Claims
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1. A semiconductor construction, comprising:
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a base; an array of semiconductor material active areas supported by the base, the array comprising columns and rows of the active areas; lines of first insulative material along the columns of the active areas, the lines directly contacting ends of the active areas;
the lines of first insulative material and rows of the active areas defining a lattice;sections of second insulative material at locations between the rows and lines of the lattice, such that said sections alternate with active areas along the columns of the array; and regions of the second insulative material under the active areas;
the regions extending from opposing sides of individual active areas to entirely separate the individual active areas from the base. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor assembly, comprising:
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a line of semiconductor material, the line having a narrow regions between wide regions;
the wide regions comprising source/drain regions of transistors and the narrow regions comprising channels between the source/drain regions;first dielectric material entirely around the narrow regions; transistor gate material extending entirely around the narrow regions, and spaced form the narrow regions of the line by the first dielectric material; second dielectric material extending through the wide regions of the line and separating adjacent wide regions from one another; and third dielectric material over the wide regions of the line;
the third dielectric material being between the transistor gate material and the second dielectric material. - View Dependent Claims (9)
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Specification