FPGA having low power, fast carry chain

• US 8,044,682 B2
• Filed: 06/01/2009
• Issued: 10/25/2011
• Est. Priority Date: 06/01/2009
• Status: Active Grant

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: SiliconBlue Technologies Corp. (Lattice Semiconductor Corporation)
• Inventors: Birkner, John, Chan, Andrew Ka Lab
• Primary Examiner(s): Ismail; Shawki
• Assistant Examiner(s): Hammond; Crystal L
• Application Number:
  US12/476,155
• Publication Number:
  US 20100301898A1
• Time in Patent Office: 876 Days
• Field of Search: 326 38- 41, 708/708, 708/707, 708/710
• US Class Current: 326/41
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17784 for supply voltage

Abstract

An in-FPGA carry chain is provided that does not exhibit significant leakage current. In particular, parts of the carry chain can be switched on/off when desired. In this manner, carry chain parts can have their leakage currents substantially disabled when they are not in use, thus saving power. Additionally, there is provided a carry chain whose logic is separate from the other parts (e.g., LUTs) of the logic blocks that perform the remaining arithmetic functions, and whose inputs are the input data to be added, rather than data that is output in delayed fashion from the other parts (e.g., LUTs) of the logic blocks. Such a configuration reduces latency by allowing the carry chain to operate directly on the received input data without need to wait on results from the other parts (e.g., LUTs) of the logic blocks.

Claims

1. A field programmable gate array (FPGA), comprising:

carry logic unit having a logic portion configured to execute a carry bit generating operation, the carry logic unit comprising an empowerment portion having a power voltage supplying terminal and a power sinking terminal, the empowerment portion being structured to support flow therethrough of an empowering current flowing through and empowering the carry bit generating operations of the logic portion of the carry logic unit when said carry bit generating operations are active, the empowering current flowing from the power voltage supplying terminal to the power sinking terminal;

wherein the empowerment portion of the carry logic unit includes a unit empowering/depowering switching transistor connected to the power sinking terminal of the carry logic unit and structured and disposed so as to support flow of the empowering current through the switching transistor; and

a programmable, empowerment/depowerment control signal provider connected to a gate terminal of the switching transistor and programmably configurable to provide depowering control signal to the gate terminal which causes the empowering/depowering switching transistor to interrupt the flow of the empowering current through the logic portion of the carry logic unit such that flow of leakage current through the logic portion is disabled when the flow of the empowering current is interrupted in response to provision of the depowering control signal to the gate terminal.

2. The FPGA of claim 1, wherein the leakage current is disabled when the carry logic unit is not being used.

3. The FPGA of claim 1,

wherein a first input bit supplied to the first input terminal of the carry logic unit is denoted as an i0 input, a second input bit supplied to the second input terminal of the carry logic unit is denoted as an i1 input, an output bit output from the output terminal of the carry logic unit is denoted as a CO output, and a third input bit supplied to the third input terminal of the carry logic unit is denoted as a Ci input;

and

wherein the carry logic unit is further configured to perform a carry bit generating function denoted by the Boolean expression;

CO=i0*i1+i0*Ci+i1*Ci.

4. A field programmable gate array (FPGA) having a plurality of configurable logic blocks (CLBs) each comprising:

a lookup table (LUT) having first and second data input terminals connected to receive respective first and second data signals transmitted thereto as inputs usable by a lookup function implemented in the LUT, and an output terminal for outputting a LUT result signal that is generated by the LUT based on the implemented lookup function of the LUT; and

carry logic unit configured to perform carry bit generating operations that produce carry bits corresponding to carry input signals received by the carry logic unit, the carry logic unit having first, second and third carry logic input terminals for receiving the carry input signals and a carry output terminal for outputting the produced carry bits;

wherein the first and second carry logic input terminals of the carry logic unit are connected respectively to the first and second data input terminals of the lookup table, wherein the plurality of configurable logic blocks (CLBs) includes a first CLB and a second CLB;

wherein the respective lookup tables of the CLBs each includes a respective third data input terminal connected to receive respective third data signal transmitted thereto as an input usable by the respective lookup function implemented in the corresponding LUT of the respective CLB; and

wherein the carry output terminal of the carry logic unit of the first CLB is programmably connectable to the third input terminal of the lookup table of the second CLB.

5. The FPGA of claim 4, wherein the lookup table is a 4-input lookup table.

6. The FPGA of claim 4:

wherein the respective lookup table of each CLB that participates in an arithmetic summation process has implemented as part of its respective lookup function, an exclusive OR function (XOR function).

7. The FPGA of claim 4:

wherein the plurality of configurable logic blocks (CLBs) includes a first CLB and a second CLB; and

wherein the third carry logic input terminal of a respective carry logic unit in the second CLB is connected to the respective carry output terminal of the respective carry logic unit in the first CLB.

8. A field programmable gate array (FPGA) circuit comprising:

a plurality of programmable lookup tables (LUTs) each having a respective LUT output terminal and respective first, second and third LUT input terminals disposed for receiving corresponding first, second and third LUT input term signals of the respective LUT;

a carry bits generating chain having a plurality of carry bit generating units, each carry bit generating unit being associated with one of the LUTs and each carry bit generating unit having a respective unit output terminal and respective first, second and third carry unit input terminals disposed for receiving corresponding first, second and third carry input term signals of the respective carry bit generating unit, where the third carry unit input terminal of each carry bit generating unit in a continuous portion of the chain is connected to the unit output terminal of the previous unit in the chain,

wherein the first and second carry unit input terminals of each unit are coupled to receive same respective first and second input signals as corresponding first and second LUT input terminals of the associated LUT, and

wherein each carry bit generating unit includes a power cut off circuit configured to selectively cut off power consumption of a carry bit generating logic portion of the unit in response to a received depowering control signal, which depowering control signal is indicative of the respective carry bit generating unit not being used for carry bit generation.

9. The FPGA circuit of claim 8 wherein:

the first and second carry unit input terminals of each unit are coupled to receive said same respective first and second input signals at a same time as they are received by the corresponding first and second LUT input terminals of the associated LUT.

10. The FPGA circuit of claim 8 wherein:

the third LUT input terminal of each given LUT is programmably couplable by way of a programmable coupling point to the unit output terminal of a carry bit generating unit associated with a different LUT.

11. The FPGA circuit of claim 10 wherein:

the depowering control signal is supplied to the power cut off circuit of each respective carry bit generating unit from a programmable control signal supplying point of the FPGA circuit.

12. The FPGA circuit of claim 11 wherein:

each carry bit generating unit has its own respective programmable control signal supplying point for supplying the corresponding depowering control signal of the respective carry bit generating unit.

13. The FPGA circuit of claim 11 wherein:

the power cut off circuit of each given carry bit generating unit includes a unit empowering/depowering switching transistor connected such that a power supplying current of the unit flows through the unit empowering/depowering switching transistor.

14. The FPGA circuit of claim 13 wherein:

the unit empowering/depowering switching transistor has a source terminal connected to a current sinking terminal of the given carry bit generating unit.

15. The FPGA circuit of claim 13 wherein:

each carry bit generating unit includes a logic portion configured to carry out a respective carry bit generating operation corresponding to the Boolean logic equation;

CO=i0*i1+i0*Ci+i1*Ci

wherein CO is an output bit output by the respective unit output terminal, Ci is a carry input bit received by the third carry unit input terminal of the respective carry bit generating unit, and i0 and i1 are respective first and second addend bits respectively received by the first and second carry unit input terminals of the respective carry bit generating unit.

16. The FPGA circuit of claim 8 wherein:

each LUT has a respective fourth LUT input terminal disposed for receiving a corresponding fourth LUT input term signal of the respective LUT.

17. A field programmable gate array (FPGA) circuit comprising:

a plurality of programmable lookup tables (LUTs) each having a respective LUT output terminal and respective plurality of LUT input terminals disposed for receiving corresponding one of plural LUT input term signals of the respective LUT;

a carry bits generating chain having a plurality of carry bit generating units, each carry bit generating unit being associated with one of the LUTs and each carry bit generating unit having a respective unit output terminal and respective first, second and third carry unit input terminals disposed for receiving corresponding first, second and third carry input term signals of the respective carry bit generating unit, where the third carry unit input terminal of each carry bit generating unit in a continuous portion of the chain is connected to the unit output terminal of the previous unit in the chain,

wherein each carry bit generating unit includes a power cut off circuit configured to selectively cut off power consumption of a carry bit generating logic portion of the unit in response to a received depowering control signal, which depowering control signal is indicative of the respective carry bit generating unit not being used for carry bit generation.

18. The FPGA of claim 17 wherein:

the power cut off circuit of a given one of the carry bit generating units is configured to selectively cut off power consumption by at least an output circuit portion of the given one carry bit generating unit where the output circuit portion directly outputs to the respective unit output terminal of the given one carry bit generating unit.