Per die temperature programming for thermally efficient integrated circuit (IC) operation

• US 8,044,697 B2
• Filed: 06/29/2006
• Issued: 10/25/2011
• Est. Priority Date: 06/29/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Arabi, Tawfik, Muhtaroglu, Ali
• Primary Examiner(s): Donovan; Lincoln
• Assistant Examiner(s): POOS, JOHN W
• Application Number:
  US11/478,472
• Publication Number:
  US 20080001634A1
• Time in Patent Office: 1,944 Days
• Field of Search: 327/291, 327/299, 713/300, 713/320
• US Class Current: 327/299
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and apparatus to provide per die temperature programming for thermally efficient integrated circuit (IC) operation are described. In some embodiments, the junction temperature of an IC component is determined, e.g., to reduce power consumption and/or improve performance. Other embodiments are also described.

Claims

1. An apparatus comprising:

a storage device to store one or more bits that cause a logic to operate at a frequency level corresponding to a junction temperature of the logic; and

a frequency controller to generate a clock signal corresponding to the frequency level,

wherein a thermal design power of the logic is to be determined based on a value of a power leakage and a dynamic capacitance of the logic.

2. The apparatus of claim 1, further comprising one or more temperature sensors to detect the junction temperature.

3. The apparatus of claim 1, wherein one or more of the storage device, the frequency controller, or the logic are on a same integrated circuit die.

4. The apparatus of claim 1, wherein the one or more bits correspond to one or more predefined power states.

5. The apparatus of claim 1, wherein the storage device comprises a non-volatile storage device.

6. The apparatus of claim 1, wherein the logic operates in accordance with the clock signal.

7. The apparatus of claim 1, wherein the one or more bits correspond to a plurality of frequency levels.

8. The apparatus of claim 7, wherein the logic is capable of operating at each of the plurality of frequency levels and within a temperature range that is less than or equal to the junction temperature.

9. The apparatus of claim 1, further comprising one or more processor cores, wherein at least one of the one or more processor cores comprises the storage device, the frequency controller, and the logic.

10. The apparatus of claim 1, further comprising one or more processor cores, wherein at least one of the processor cores, the storage device, the frequency controller, and the logic are on a same integrated circuit die.

11. A method comprising:

determining a junction temperature of a logic;

storing one or more data bits corresponding to one or more frequency levels in a storage device;

generating a clock signal in accordance with at least one of the frequency levels that causes the logic to operate at a temperature that is equal to or less than the junction temperature; and

determining at least one of;

a thermal design power (TDP) of the logic based on stored values corresponding to power leakage and dynamic capacitance of the logic or a value of dynamic capacitance of the logic during operation of the logic.

12. The method of claim 11, further comprising determining the junction temperature based on a thermal design power (TDP), an ambient temperature, and a junction to ambient thermal resistance of the logic.

13. The method of claim 11, further comprising determining a value of power leakage generated during operation of the logic.

14. The method of claim 11, further comprising determining a thermal design power (TDP) of the logic during operation of the logic.

15. The method of claim 11, further comprising determining the junction temperature based on stored values corresponding to a thermal design power (TDP), an ambient temperature, and a junction to ambient thermal resistance of the logic.

16. A system comprising:

a display device to display one or more images;

a non-volatile memory to store one or more bits corresponding to one or more frequency levels;

a programmable frequency controller coupled to the display device and configured to generate a clock signal in accordance with at least one of the frequency levels to cause a logic to operate at a temperature that is equal to or less than a junction temperature of the logic; and

a plurality of processor cores to generate data corresponding to the one or more images.

17. The system of claim 16, wherein the display device comprises a liquid crystal display (LCD) device.

18. A computer-readable medium comprising one or more instructions that when executed on a processor configure the processor to:

determine a junction temperature of a logic;

store one or more data bits that cause the logic to operate at a frequency level corresponding to the junction temperature of the logic; and

determine the thermal design power of the logic based on a value of a power leakage and a dynamic capacitance of the logic.

19. The computer-readable medium of claim 18, further comprising one or more instructions that configure the processor to determine the junction temperature based on a thermal design power (TDP), an ambient temperature, and a junction to ambient thermal resistance of the logic.