MEMS power inductor

• US 8,044,755 B2
• Filed: 04/09/2008
• Issued: 10/25/2011
• Est. Priority Date: 04/09/2008
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Smeys, Peter, Johnson, Peter
• Primary Examiner(s): Mai; Anh
• Assistant Examiner(s): Baisa; Joselito
• Application Number:
  US12/082,209
• Publication Number:
  US 20090256667A1
• Time in Patent Office: 1,294 Days
• Field of Search: 336/200, 336/223, 336/232, 257/531
• US Class Current: 336/200
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 2017/0066 with a magnetic layer
• CPC Class Codes: H01F 2017/0086 on semiconductor substrate
• CPC Class Codes: H01F 41/046 structurally combined with ferromagnetic material
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: Y10T 29/4902 Electromagnet, transformer or inductor
• CPC Class Codes: Y10T 29/49073 by assembling coil and core
• CPC Class Codes: Y10T 29/49075 including permanent magnet or core
• CPC Class Codes: Y10T 29/49124 On flat or curved insulated base, e.g., printed circuit, etc.
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.

Abstract

A scalable MEMS inductor is formed on the top surface of a semiconductor die. The MEMS inductor includes a plurality of magnetic lower laminations, a circular trace that lies over and spaced apart from the magnetic lower laminations, and a plurality of upper laminations that lie over and spaced apart from the circular trace.

Claims

1. A semiconductor inductor comprising:

a plurality of lower magnetic structures, each lower magnetic structure being spaced apart and electrically isolated from each other lower magnetic structure, and having a top surface;

a non-conductive structure, the non-conductive structure touching the top surface of each lower magnetic structure;

a conductive trace, the conductive trace touching the non-conductive structure, and lying directly over each of the lower magnetic structures; and

a plurality of upper magnetic structures, each upper magnetic structure being spaced apart and electrically isolated from each other upper magnetic structure, and touching the non-conductive structure, no portion of any upper magnetic structure touching any portion of a lower magnetic structure, no portion of any upper magnetic structure touching any portion of the conductive trace.

2. The semiconductor inductor of claim 1 wherein each upper magnetic structure lies horizontally adjacent to and spaced apart from the conductive trace.

3. The semiconductor inductor of claim 2 wherein the conductive trace is spaced apart and electrically isolated from each of the plurality of lower magnetic structures.

4. The semiconductor inductor of claim 3 wherein the conductive trace is circular.

5. The semiconductor inductor of claim 3 wherein the plurality of lower magnetic structures lie above and extend around a periphery of a metal interconnect structure, the metal interconnect structure including a conductive structure, the conductive trace being electrically connected to the conductive structure.

6. The semiconductor inductor of claim 3 wherein the non-conductive structure includes a non-conductive layer and a non-conductive base mold.

7. The semiconductor inductor of claim 6 wherein the non-conductive layer and the non-conductive base mold are a same material.

8. The semiconductor inductor of claim 3 wherein the plurality of lower magnetic structures each includes permalloy.

9. The semiconductor inductor of claim 3 wherein the conductive trace includes copper.

10. The semiconductor inductor of claim 3 wherein each upper magnetic structure of the plurality of upper magnetic structures lies vertically over the conductive trace.

11. The semiconductor inductor of claim 10 wherein the conductive trace is circular.

12. The semiconductor inductor of claim 10 wherein the plurality of lower magnetic structures lie above and extend around a periphery of a metal interconnect structure, the metal interconnect structure including a conductive structure, the conductive trace being electrically connected to the conductive structure.

13. The semiconductor inductor of claim 10 wherein the top surface of each of the plurality of lower magnetic structures lies substantially in a single plane.

14. The semiconductor inductor of claim 10 wherein each of the plurality of lower magnetic structures lies directly below a corresponding upper magnetic structure of the plurality of upper magnetic structures.

15. The semiconductor inductor of claim 10 wherein the plurality of lower magnetic structures and the plurality of upper magnetic structures form a magnetic core structure.

16. The semiconductor inductor of claim 1 wherein the conductive trace is spaced apart and electrically isolated from each of the plurality of lower magnetic structures, and each of the plurality of upper magnetic structures lies above the conductive trace.

17. The semiconductor inductor of claim 16 wherein the conductive trace is circular.

18. The semiconductor inductor of claim 16 wherein the plurality of lower magnetic structures lie above and extend around a periphery of a metal interconnect structure, the metal interconnect structure including a conductive structure, the conductive trace being electrically connected to the conductive structure.

19. The semiconductor inductor of claim 16 wherein each upper magnetic structure includes an inverted U shape.

20. The semiconductor inductor of claim 19 wherein the conductive trace lies within the inverted U shape.