Decoding apparatus and control method thereof

• US 8,044,831 B2
• Filed: 01/08/2010
• Issued: 10/25/2011
• Est. Priority Date: 01/16/2009
• Status: Active Grant

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Hara, Yuji, Ishikawa, Hisashi
• Primary Examiner(s): YOUNG, BRIAN K
• Application Number:
  US12/684,171
• Publication Number:
  US 20100182171A1
• Time in Patent Office: 655 Days
• Field of Search: 341/59, 341/65, 341/67, 382/238, 375/240.01, 348/500
• US Class Current: 341/67
• CPC Class Codes: H03M 7/425 for the decoding process only
• CPC Class Codes: H03M 7/48 alternating with other codes during the code conversion process, e.g. run-length coding being performed only as long as sufficientlylong runs of digits of the same kind are present

Abstract

The invention provides a decoding apparatus which guarantees a decoding speed of a predetermined unit. To this end, the decoding apparatus includes a shifter which detects a start bit of a codeword from coded data, a table which stores decode values of a plurality of symbol data at one address, a table which is used to store a shift amount of the shifter, a table which generates a data length of the decode values of the plurality of symbol data, a decoder which is used to generate an address of the first table from the coded data, a decoder which is used to generate an address of the second and third tables from the coded data, and a packer which couples or separates the decoded values of the plurality of symbol data to data for the predetermined fixed number of bits.

Claims

1. A decoding apparatus, comprising:

a shifter which detects a start bit of a codeword from coded data;

a memory which stores a first table, a second table and a third table, wherein the first table stores decode values of a plurality of symbol data at one address, the second table stores a shift amount of the shifter, and the third table is used to generate a data length of the decode values of the plurality of symbol data;

a first decoder which is used to generate an address of the first table from the coded data;

a second decoder which is used to generate an address of the second and third tables from the coded data; and

an output unit which is used to couple or separate the decode values of the plurality of symbol data to data for a predetermined fixed number of bits;

wherein the decoding apparatus decodes coded data generated by executing variable length coding to have a pixel block including a plurality of pixels (the number of pixels N) as a unit, and

wherein letting P (bits) be a code size of the pixel block, T (pixels/clock cycle) be a target throughput, x (bits/clock cycle) be a code size to be processed per clock cycle, and y (pixels/clock cycle) be the number of pixels to be processed per clock cycle, at least either of;

x≧

(P/N)×

T

and

y≧

T

is satisfied.

2. The apparatus according to claim 1, wherein the variable length coding is runlength coding.

4. A non-transitory computer-readable storage medium storing a computer program for making a computer function as a decoding apparatus according to claim 1 when the computer loads and executes the computer program.

3. A method of controlling a decoding apparatus, comprising:

a shift step of detecting a start bit of a codeword from coded data;

a first decode step of generating an address of a first table from the coded data;

a second decode step of generating an address of second and third tables from the coded data; and

an output step of coupling or separating decode values of a plurality of symbol data to data for a predetermined fixed number of bits;

wherein the first table stores the decode values of the plurality of symbol data at one address, the second table stores a shift amount of a shifter, and the third table is used to generate a data length of the decode values of the plurality of symbol data;

wherein the method decodes coded data generated by executing variable length coding to have a pixel block including a plurality of pixels (the number of pixels N) as a unit, and

wherein letting P (bits) be a code size of the pixel block, T (pixels/clock cycle) be a target throughput, x (bits/clock cycle) be a code size to be processed per clock cycle, and y (pixels/clock cycle) be the number of pixels to be processed per clock cycle, at least either of;

x≧

(P/N)×

T

and

y≧

T

is satisfied.

5. A decoding apparatus for decoding coded data, which is generated by variable length coding, and outputting a plurality of pixel data, the decoding apparatus comprising:

a shifter which detects a start bit of a codeword from coded data;

a memory storing a first table which stores decode values of a plurality of symbol data at one address, a second table which stores a shift amount of the shifter, and a third table which is used to generate a data length of the plurality of symbol data;

a first decoder which is used to generate an address of the first table from the coded data;

a second decoder which is used to generate an address of the second and third tables from the coded data; and

an output unit which is used to couple or separate the decode values of the plurality of symbol data to data for a predetermined fixed number of bits.

6. The apparatus according to claim 5, wherein the variable length coding is runlength coding.

7. The apparatus according to claim 6, wherein the first table stores until a pixel next to a last change point except for decoding of only one symbol.

8. The apparatus according to claim 6, wherein elements of the first table store values under an assumption that a decode value of an immediately preceding pixel is 1 or 0.

9. The apparatus according to claim 8, wherein a decode value based on the first table is output intact when a decode value of an immediately preceding pixel is equal to the assumed value, and a value of the first table is inverted and output when a decode value of an immediately preceding pixel is different from the assumed value.

10. The apparatus according to claim 5, wherein the output unit continuously outputs data of a pixel next to a last change point upon coupling a part exceeding the last change point.

11. The apparatus according to claim 5, wherein the second decoder generates an address from predetermined bits of coded data corresponding to individual symbols.

12. The apparatus according to claim 5, wherein elements of the third table store the shift amount, a base value required to calculate a data length after the symbol data is decoded, and a reference bit position of the detected coded data.

13. The apparatus according to claim 12, wherein the data length of the symbol data is calculated using a sum total of the base value and a value of coded data at the reference bit position.

14. A method of controlling a decoding apparatus for decoding coded data, which is generated by variable length coding, and outputting a plurality of pixel data, wherein the decoding apparatus includes:

a first table which stores decode values of a plurality of symbol data at one address;

a second table which stores a shift amount of a shifter; and

a third table which is used to generate a data length of the plurality of symbol data;

the method comprising;

a shift step of detecting a start bit of a codeword from coded data;

a first decode step of generating an address of the first table from the coded data;

a second decode step of generating an address of the second and third tables from the coded data; and

an output step of coupling or separating the decode values of the plurality of symbol data to data for a predetermined fixed number of bits.

15. A non-transitory computer-readable storage medium storing a computer program for making a computer execute respective steps of a control method according to claim 14 to function as a decoding apparatus when the computer loads and executes the computer program.