Liquid crystal display device

• US 8,045,072 B2
• Filed: 02/05/2008
• Issued: 10/25/2011
• Est. Priority Date: 05/27/2004
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Ahn, Byung Chul
• Primary Examiner(s): Vu; Phu
• Application Number:
  US12/068,361
• Publication Number:
  US 20080143903A1
• Time in Patent Office: 1,358 Days
• Field of Search: 349 38- 39, 349/192
• US Class Current: 349/38
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136236 using a grey or half tone lithographic process
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

A thin film transistor substrate of a LCD device and a fabricating method thereof are disclosed for simplifying a fabricating process and enlarging a capacitance value of a storage capacitor without any reduction of aperture ratio. The LCD device includes: a double-layered gate line having a first transparent conductive layer and a second opaque conductive layer, the second opaque conductive layer have a step coverage; a gate insulation layer film on the gate line; a data line crossing the gate line to define a pixel region; a TFT connected to the gate line and the data line; a pixel electrode connected to the TFT via a contact hole of a protective film on the TFT; and a storage capacitor overlapping the pixel electrode and having a lower storage electrode formed of the first transparent conductive layer.

Claims

1. A liquid crystal display device, comprising:

a double-layered gate line having a first transparent conductive layer and a second opaque conductive layer;

a gate insulation film on the gate line;

a data line crossing the gate line to define a pixel region;

a thin film transistor connected to the gate line and the data line;

a pixel electrode connected to the thin film transistor via a contact hole of a protective film on the thin film transistor; and

a storage capacitor overlapping the pixel electrode and having a lower storage electrode extended from the first transparent conductive layer of the double-layered gate line, the pixel electrode overlapped with the lower storage electrode being an upper storage electrode.

2. The device of claim 1, wherein the lower storage electrode protrudes from the first transparent conductive layer of the gate line toward the pixel region.

3. The device of claim 1, further comprising a common line crossing the pixel electrode and the data line.

4. The device of claim 3, wherein the common line is formed of the first transparent conductive layer of the lower storage electrode.

5. The device of claim 3, wherein the common line is formed similar to the double-layer of the gate line.

6. The device of claim 5, wherein the lower storage electrode protrudes from a first conductive layer of the gate line toward the pixel region.

7. The device of claim 1, further comprising a redundancy line independently formed between the gate lines.

8. The device of claim 7, wherein the redundancy line overlaps the data line.

9. The device of claim 7, wherein the redundancy line is formed of one of the first transparent conductive layer and a double-layer of the gate line.

10. The device of claim 1, further comprising a light-shielding pattern protruded from the second conductive layer of the gate line and overlapping with both sides of the pixel electrode.

11. The device of claim 10, wherein the light-shielding pattern overlaps the lower storage electrode.

12. The device of claim 1, further comprising a gate pad including a lower gate pad electrode having a double-layer and an upper gate pad electrode connected to the lower gate pad electrode via a contact hole of the gate insulating film and the protective film, wherein the lower gate pad electrode is connected to the gate line.

13. The device of claim 1, further comprising a data pad including a lower data pad electrode connected to the data line, and an upper data pad electrode connected to the lower data pad electrode via a contact hole of the protective film.

14. The device of claim 1, wherein the gate line further includes a third conductive layer on the second conductive layer.

15. The device of claim 1, wherein a gate electrode of the thin film transistor is connected to the gate line, the gate electrode having a double-layer.