Apparatus and method for self-refreshing dynamic random access memory cells
First Claim
1. A method for low power refreshing a dynamic random access memory (DRAM) having cells arranged in rows and columns, comprising:
- refreshing the cells in a one cell-per-bit mode at a first frequency during a normal mode of operation where the cells are read and written in the one cell-per-bit mode;
entering a self-refresh mode for reducing refresh power consumption;
generating refresh addresses including a starting refresh address for selecting a first row of cells to be refreshed, by an address counter;
executing a dummy refresh cycle in response to a comparison between the starting address and a predetermined address;
refreshing the cells in a two cell-per-bit mode at a second frequency lower than the first frequency during the self-refresh mode in response to the refresh addresses and beginning at the starting refresh address; and
,exiting the self-refresh mode to resume the normal mode of operation.
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Abstract
A dynamic random access memory (DRAM) having DRAM cells coupled to wordlines and bitlines. In a self-refresh mode, the cells coupled with the even numbered rows retain main data previously stored therein and the assistant data, which is logically opposite to the main data, is overwritten into the cells coupled with the wordlines of the odd numbered rows. When the DRAM enters the self-refresh mode, a starting refresh address for the self-refresh mode is detected. If the detected starting refresh address does not match with a predetermined correct address set for the self-refresh operation mode, a dummy refresh cycle will be established in an entry-burst self-refresh period. During the dummy refresh cycle, a dummy refresh command is added to increment an internal row address counter that provides row addresses for self-refreshing the cells of the selected wordlines within the cell array.
23 Citations
18 Claims
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1. A method for low power refreshing a dynamic random access memory (DRAM) having cells arranged in rows and columns, comprising:
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refreshing the cells in a one cell-per-bit mode at a first frequency during a normal mode of operation where the cells are read and written in the one cell-per-bit mode; entering a self-refresh mode for reducing refresh power consumption; generating refresh addresses including a starting refresh address for selecting a first row of cells to be refreshed, by an address counter; executing a dummy refresh cycle in response to a comparison between the starting address and a predetermined address; refreshing the cells in a two cell-per-bit mode at a second frequency lower than the first frequency during the self-refresh mode in response to the refresh addresses and beginning at the starting refresh address; and
,exiting the self-refresh mode to resume the normal mode of operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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Specification