Method and apparatus for programming memory cell array

• US 8,045,373 B2
• Filed: 09/29/2008
• Issued: 10/25/2011
• Est. Priority Date: 10/02/2007
• Status: Active Grant

• Current Assignee: Longitude Flash Memory Solutions, Ltd. (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Jenne, Fredrick B., Ratnakumar, Cynthia
• Primary Examiner(s): Tran, Michael
• Application Number:
  US12/240,184
• Publication Number:
  US 20090086538A1
• Time in Patent Office: 1,121 Days
• Field of Search: 365/185.02, 365/185.24
• US Class Current: 365/185.02
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

Disclosed are a method and device for programming an array of memory cells.

Claims

1. A method for reducing disturbs in an array of memory cells, comprising:

selecting a first row of the array of memory cells for a write operation, the first row comprising a first memory cell in a first column of the array of memory cells and a second memory cell in a second column of the array of memory cells, wherein the first memory cell connected between a first bit line and a first source line and the second memory cell connected between a second bit line and a second source line, wherein each of the memory cells includes a memory transistor and a pass transistor;

connecting the first bit line to the first source line and the second bit line to the second source line, wherein the first source line is equipotential with the first bit line and the second source line is equipotential with the second bit line; and

erasing the first row of the array of memory cells.

2. The method of claim 1, further comprising programming the first memory cell and inhibiting the second memory cell.

3. The method of claim 2, wherein the second column includes a third memory cell in a second row of the array and the first column includes a fourth memory cell in the second row of the array of memory cells, wherein the third memory cell is connected between the second bit line and the second source line and the fourth memory cell is connected between the first bit line and the first source line.

4. A method for reducing disturbs in an array of memory cells, comprising:

selecting a first row of the array of memory cells for a write operation, the first row comprising a first memory cell in a first column of the array of memory cells and a second memory cell in a second column of the array of memory cells, wherein the first memory cell connected between a first bit line and a first source line and the second memory cell connected between a second bit line and a second source line;

connecting the first bit line to the first source line and the second bit line to the second source line, wherein the first source line is equipotential with the first bit line and the second source line is equipotential with the second bit line;

erasing the first row of the array of memory cells;

programming the first memory cell and inhibiting the second memory cell, wherein the second column includes a third memory cell in a second row of the array and the first column includes a fourth memory cell in the second row of the array of memory cells, wherein the third memory cell is connected between the second bit line and the second source line and the fourth memory cell is connected between the first bit line and the first source line; and

applying a first reference voltage on a first write line shared by the first memory cell and the second memory cell, wherein programming the first memory cell comprises applying a programming voltage on the first bit line, and inhibiting the second memory cell comprises applying an inhibit voltage on the second bit line.

5. The method of claim 4, further comprising:

applying the programming voltage on a first select line shared by the first memory cell and the second memory cell;

applying the programming voltage on a second write line shared by the third memory cell and the fourth memory cell; and

applying the inhibit voltage on a second select line shared by the third memory cell and the fourth memory cell.

6. The method of claim 5, further comprising applying a second reference voltage on the first write line, wherein erasing the first row of the memory array comprises applying an erase voltage on the first bit line and the second bit line.

7. The method of claim 6, further comprising:

applying the second reference voltage on the second write line;

applying the inhibit voltage on the second select line; and

applying a hold-off voltage on the first select line.

8. The method of claim 5, wherein each of the first, second, third and fourth memory cells includes a non-volatile stored-charge memory transistor and a field effect pass transistor, having a common body connected to one of the programming voltage and the erase voltage, the memory transistor having a drain connected to a respective bit line, a control gate connected to a respective write line and a source connected to a drain of the pass transistor, the pass transistor having a control gate connected to a respective select line and a source connected to a respective source line.

9. The method of claim 8, wherein the memory transistor comprises one of a floating gate transistor and a trapped-charge SONOS-type transistor.

10. An apparatus, comprising:

a memory array comprising memory cells arranged in rows and columns; and

a memory controller coupled to the memory array, comprising;

a row controller configured to select a first row of the memory array for a write operation and to deselect a second row of the memory array, wherein the first row comprises a first memory cell coupled between a first bit line and a first source line in a first column of the memory array and a second memory cell coupled between a second bit line and a second source line in a second column of the memory array, wherein each of the memory cells includes a memory transistor and a pass transistor; and

a column controller configured to connect the first bit line to the first source line and to connect the second bit line to the second source line, the column controller further configured to erase the first row of the memory array.

11. The apparatus of claim 10, wherein the memory controller is further configured to program the first memory cell and to inhibit the second memory cell from programming.

12. The apparatus of claim 11, wherein the second row comprises a third memory cell coupled between the second bit line and the second source line and a fourth memory cell coupled between the first bit line and the first source line.

13. An apparatus, comprising:

a memory array comprising memory cells arranged in rows and columns; and

a memory controller coupled to the memory array, comprising;

a row controller configured to select a first row of the memory array for a write operation and to deselect a second row of the memory array, wherein the first row comprises a first memory cell coupled between a first bit line and a first source line in a first column of the memory array and a second memory cell coupled between a second bit line and a second source line in a second column of the memory array; and

a column controller configured to connect the first bit line to the first source line and to connect the second bit line to the second source line, the column controller further configured to erase the first row of the memory array, wherein the memory controller is further configured to program the first memory cell and to inhibit the second memory cell from programming, wherein the second row comprises a third memory cell coupled between the second bit line and the second source line and a fourth memory cell coupled between the first bit line and the first source line, wherein the row controller is configured to apply a first reference voltage on a first write line shared by the first memory cell and the second memory cell, wherein to program the first memory cell the column controller is configured to apply a programming voltage on the first bit line, and wherein to inhibit the second memory cell the column controller is configured to apply an inhibit voltage on the second bit line.

14. The apparatus of claim 13, wherein the row controller is configured to:

apply the programming voltage on a first select line shared by the first memory cell and the second memory cell and on a second write line shared by the third memory cell and the fourth memory cell; and

to

apply the inhibit voltage on a second select line shared by the third memory cell and the fourth memory cell.

15. The apparatus of claim 14, wherein the row controller is further configured to apply a second reference voltage on the first write line, wherein to erase the first row of the memory array, the column controller is configured to apply an erase voltage on the first bit line and the second bit line.

16. The apparatus of claim 15, wherein the row controller is further configured to:

apply the second reference voltage on the second write line;

to

apply the inhibit voltage on the second select line; and

to

apply a hold-off voltage on the first select line.

17. The apparatus of claim 14, wherein each of the first, second, third and fourth memory cells includes a non-volatile stored-charge memory transistor and a field effect pass transistor, having a common body connected to one of the programming voltage and the erase voltage, the memory transistor having a drain connected to a respective bit line, a control gate connected to a respective write line and a source connected to a drain of the pass transistor, the pass transistor having a control gate connected to a respective select line and a source connected to a respective source line.

18. The apparatus of claim 17, wherein the memory transistor comprises one of a floating gate transistor and a trapped-charge SONOS-type transistor.

19. An apparatus, comprising:

means for selecting a row of memory cells in a memory array for a write operation, wherein each of the memory cells includes a memory transistor and a pass transistor;

means for selectively connecting source lines of the memory cells to bit lines of the memory cells to conform the voltages on the source lines to voltages on the bit lines; and

means for selectively programming and erasing memory cells in the row of memory cells.

20. The apparatus of claim 19, wherein the means for selectively tracking the source line voltages to the bit line voltages comprises means for selectively connecting and disconnecting the source lines to the bit lines.